1from __future__ import print_function 2import lldb 3from lldbsuite.test.lldbtest import * 4from lldbsuite.test.decorators import * 5from gdbclientutils import * 6 7class MyResponder(MockGDBServerResponder): 8 def qXferRead(self, obj, annex, offset, length): 9 if annex == "target.xml": 10 return """<?xml version="1.0"?> 11 <target version="1.0"> 12 <architecture>i386:x86-64</architecture> 13 <feature name="org.gnu.gdb.i386.core"> 14 15 <flags id="i386_eflags" size="4"> 16 <field name="CF" start="0" end="0"/> 17 <field name="" start="1" end="1"/> 18 <field name="PF" start="2" end="2"/> 19 <field name="AF" start="4" end="4"/> 20 <field name="ZF" start="6" end="6"/> 21 <field name="SF" start="7" end="7"/> 22 <field name="TF" start="8" end="8"/> 23 <field name="IF" start="9" end="9"/> 24 <field name="DF" start="10" end="10"/> 25 <field name="OF" start="11" end="11"/> 26 <field name="NT" start="14" end="14"/> 27 <field name="RF" start="16" end="16"/> 28 <field name="VM" start="17" end="17"/> 29 <field name="AC" start="18" end="18"/> 30 <field name="VIF" start="19" end="19"/> 31 <field name="VIP" start="20" end="20"/> 32 <field name="ID" start="21" end="21"/> 33 </flags> 34 35 <reg name="rax" bitsize="64" regnum="0" type="int" group="general"/> 36 <reg name="rbx" bitsize="64" regnum="1" type="int" group="general"/> 37 <reg name="rcx" bitsize="64" regnum="2" type="int" group="general"/> 38 <reg name="rdx" bitsize="64" regnum="3" type="int" group="general"/> 39 <reg name="rsi" bitsize="64" regnum="4" type="int" group="general"/> 40 <reg name="rdi" bitsize="64" regnum="5" type="int" group="general"/> 41 <reg name="rbp" bitsize="64" regnum="6" type="data_ptr" group="general"/> 42 <reg name="rsp" bitsize="64" regnum="7" type="data_ptr" group="general"/> 43 <reg name="r8" bitsize="64" regnum="8" type="int" group="general"/> 44 <reg name="r9" bitsize="64" regnum="9" type="int" group="general"/> 45 <reg name="r10" bitsize="64" regnum="10" type="int" group="general"/> 46 <reg name="r11" bitsize="64" regnum="11" type="int" group="general"/> 47 <reg name="r12" bitsize="64" regnum="12" type="int" group="general"/> 48 <reg name="r13" bitsize="64" regnum="13" type="int" group="general"/> 49 <reg name="r14" bitsize="64" regnum="14" type="int" group="general"/> 50 <reg name="r15" bitsize="64" regnum="15" type="int" group="general"/> 51 <reg name="rip" bitsize="64" regnum="16" type="code_ptr" group="general"/> 52 <reg name="eflags" bitsize="32" regnum="17" type="i386_eflags" group="general"/> 53 54 <reg name="cs" bitsize="32" regnum="18" type="int" group="general"/> 55 <reg name="ss" bitsize="32" regnum="19" type="int" group="general"/> 56 <reg name="ds" bitsize="32" regnum="20" type="int" group="general"/> 57 <reg name="es" bitsize="32" regnum="21" type="int" group="general"/> 58 <reg name="fs" bitsize="32" regnum="22" type="int" group="general"/> 59 <reg name="gs" bitsize="32" regnum="23" type="int" group="general"/> 60 61 <reg name="st0" bitsize="80" regnum="24" type="i387_ext" group="float"/> 62 <reg name="st1" bitsize="80" regnum="25" type="i387_ext" group="float"/> 63 <reg name="st2" bitsize="80" regnum="26" type="i387_ext" group="float"/> 64 <reg name="st3" bitsize="80" regnum="27" type="i387_ext" group="float"/> 65 <reg name="st4" bitsize="80" regnum="28" type="i387_ext" group="float"/> 66 <reg name="st5" bitsize="80" regnum="29" type="i387_ext" group="float"/> 67 <reg name="st6" bitsize="80" regnum="30" type="i387_ext" group="float"/> 68 <reg name="st7" bitsize="80" regnum="31" type="i387_ext" group="float"/> 69 70 <reg name="fctrl" bitsize="32" regnum="32" type="int" group="float"/> 71 <reg name="fstat" bitsize="32" regnum="33" type="int" group="float"/> 72 <reg name="ftag" bitsize="32" regnum="34" type="int" group="float"/> 73 <reg name="fiseg" bitsize="32" regnum="35" type="int" group="float"/> 74 <reg name="fioff" bitsize="32" regnum="36" type="int" group="float"/> 75 <reg name="foseg" bitsize="32" regnum="37" type="int" group="float"/> 76 <reg name="fooff" bitsize="32" regnum="38" type="int" group="float"/> 77 <reg name="fop" bitsize="32" regnum="39" type="int" group="float"/> 78 </feature> 79 </target>""", False 80 else: 81 return None, False 82 83 def qC(self): 84 return "QC1" 85 86 def haltReason(self): 87 return "T05thread:00000001;06:9038d60f00700000;07:98b4062680ffffff;10:c0d7bf1b80ffffff;" 88 89 def readRegister(self, register): 90 regs = {0x0: "00b0060000610000", 91 0xa: "68fe471c80ffffff", 92 0xc: "60574a1c80ffffff", 93 0xd: "18f3042680ffffff", 94 0xe: "be8a4d7142000000", 95 0xf: "50df471c80ffffff", 96 0x10: "c0d7bf1b80ffffff" } 97 if register in regs: 98 return regs[register] 99 else: 100 return "0000000000000000" 101 102class TestTargetXMLArch(GDBRemoteTestBase): 103 104 @skipIfXmlSupportMissing 105 @expectedFailureAll(archs=["i386"]) 106 @skipIfRemote 107 def test(self): 108 """ 109 Test lldb's parsing of the <architecture> tag in the target.xml register 110 description packet. 111 """ 112 self.server.responder = MyResponder() 113 interp = self.dbg.GetCommandInterpreter() 114 result = lldb.SBCommandReturnObject() 115 if self.TraceOn(): 116 self.runCmd("log enable gdb-remote packets") 117 self.addTearDownHook( 118 lambda: self.runCmd("log disable gdb-remote packets")) 119 120 target = self.dbg.CreateTarget('') 121 self.assertEqual('', target.GetTriple()) 122 process = self.connect(target) 123 if self.TraceOn(): 124 interp.HandleCommand("target list", result) 125 print(result.GetOutput()) 126 self.assertTrue(target.GetTriple().startswith('x86_64-unknown-unknown')) 127 128 @skipIfXmlSupportMissing 129 @skipIfRemote 130 def test_register_augmentation(self): 131 """ 132 Test that we correctly associate the register info with the eh_frame 133 register numbers. 134 """ 135 136 target = self.createTarget("basic_eh_frame.yaml") 137 self.server.responder = MyResponder() 138 139 process = self.connect(target) 140 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 141 [lldb.eStateStopped]) 142 self.filecheck("image show-unwind -n foo", __file__, 143 "--check-prefix=UNWIND") 144# UNWIND: eh_frame UnwindPlan: 145# UNWIND: row[0]: 0: CFA=rsp+128 => rip=[CFA-8] 146