1//===-- PPCScheduleG5.td - PPC G5 Scheduling Definitions ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the itinerary class data for the G5 (970) processor. 10// 11//===----------------------------------------------------------------------===// 12 13def G5_BPU : FuncUnit; // Branch unit 14def G5_SLU : FuncUnit; // Store/load unit 15def G5_SRU : FuncUnit; // special register unit 16def G5_IU1 : FuncUnit; // integer unit 1 (simple) 17def G5_IU2 : FuncUnit; // integer unit 2 (complex) 18def G5_FPU1 : FuncUnit; // floating point unit 1 19def G5_FPU2 : FuncUnit; // floating point unit 2 20def G5_VPU : FuncUnit; // vector permutation unit 21def G5_VIU1 : FuncUnit; // vector integer unit 1 (simple) 22def G5_VIU2 : FuncUnit; // vector integer unit 2 (complex) 23def G5_VFPU : FuncUnit; // vector floating point unit 24 25def G5Itineraries : ProcessorItineraries< 26 [G5_IU1, G5_IU2, G5_SLU, G5_BPU, G5_FPU1, G5_FPU2, 27 G5_VFPU, G5_VIU1, G5_VIU2, G5_VPU], [], [ 28 InstrItinData<IIC_IntSimple , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 29 InstrItinData<IIC_IntGeneral , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 30 InstrItinData<IIC_IntCompare , [InstrStage<3, [G5_IU1, G5_IU2]>]>, 31 InstrItinData<IIC_IntDivD , [InstrStage<68, [G5_IU1]>]>, 32 InstrItinData<IIC_IntDivW , [InstrStage<36, [G5_IU1]>]>, 33 InstrItinData<IIC_IntMFFS , [InstrStage<6, [G5_IU2]>]>, 34 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G5_VFPU]>]>, 35 InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, 36 InstrItinData<IIC_IntMulHD , [InstrStage<7, [G5_IU1, G5_IU2]>]>, 37 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G5_IU1, G5_IU2]>]>, 38 InstrItinData<IIC_IntMulHWU , [InstrStage<5, [G5_IU1, G5_IU2]>]>, 39 InstrItinData<IIC_IntMulLI , [InstrStage<4, [G5_IU1, G5_IU2]>]>, 40 InstrItinData<IIC_IntRFID , [InstrStage<1, [G5_IU2]>]>, 41 InstrItinData<IIC_IntRotateD , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 42 InstrItinData<IIC_IntRotateDI , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 43 InstrItinData<IIC_IntRotate , [InstrStage<4, [G5_IU1, G5_IU2]>]>, 44 InstrItinData<IIC_IntShift , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 45 InstrItinData<IIC_IntTrapD , [InstrStage<1, [G5_IU1, G5_IU2]>]>, 46 InstrItinData<IIC_IntTrapW , [InstrStage<1, [G5_IU1, G5_IU2]>]>, 47 InstrItinData<IIC_BrB , [InstrStage<1, [G5_BPU]>]>, 48 InstrItinData<IIC_BrCR , [InstrStage<4, [G5_BPU]>]>, 49 InstrItinData<IIC_BrMCR , [InstrStage<2, [G5_BPU]>]>, 50 InstrItinData<IIC_BrMCRX , [InstrStage<3, [G5_BPU]>]>, 51 InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G5_SLU]>]>, 52 InstrItinData<IIC_LdStLoad , [InstrStage<3, [G5_SLU]>]>, 53 InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>, 54 InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G5_SLU]>]>, 55 InstrItinData<IIC_LdStStore , [InstrStage<3, [G5_SLU]>]>, 56 InstrItinData<IIC_LdStDSS , [InstrStage<10, [G5_SLU]>]>, 57 InstrItinData<IIC_LdStICBI , [InstrStage<40, [G5_SLU]>]>, 58 InstrItinData<IIC_LdStSTFD , [InstrStage<4, [G5_SLU]>]>, 59 InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [G5_SLU]>]>, 60 InstrItinData<IIC_LdStLD , [InstrStage<3, [G5_SLU]>]>, 61 InstrItinData<IIC_LdStLDU , [InstrStage<3, [G5_SLU]>]>, 62 InstrItinData<IIC_LdStLDUX , [InstrStage<3, [G5_SLU]>]>, 63 InstrItinData<IIC_LdStLDARX , [InstrStage<11, [G5_SLU]>]>, 64 InstrItinData<IIC_LdStLFD , [InstrStage<3, [G5_SLU]>]>, 65 InstrItinData<IIC_LdStLFDU , [InstrStage<5, [G5_SLU]>]>, 66 InstrItinData<IIC_LdStLFDUX , [InstrStage<5, [G5_SLU]>]>, 67 InstrItinData<IIC_LdStLHA , [InstrStage<5, [G5_SLU]>]>, 68 InstrItinData<IIC_LdStLHAU , [InstrStage<5, [G5_SLU]>]>, 69 InstrItinData<IIC_LdStLHAUX , [InstrStage<5, [G5_SLU]>]>, 70 InstrItinData<IIC_LdStLMW , [InstrStage<64, [G5_SLU]>]>, 71 InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G5_SLU]>]>, 72 InstrItinData<IIC_LdStLWA , [InstrStage<5, [G5_SLU]>]>, 73 InstrItinData<IIC_LdStLWARX , [InstrStage<11, [G5_SLU]>]>, 74 InstrItinData<IIC_LdStSLBIA , [InstrStage<40, [G5_SLU]>]>, // needs work 75 InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [G5_SLU]>]>, 76 InstrItinData<IIC_LdStSTD , [InstrStage<3, [G5_SLU]>]>, 77 InstrItinData<IIC_LdStSTU , [InstrStage<3, [G5_SLU]>]>, 78 InstrItinData<IIC_LdStSTUX , [InstrStage<3, [G5_SLU]>]>, 79 InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [G5_SLU]>]>, 80 InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [G5_SLU]>]>, 81 InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [G5_SLU]>]>, 82 InstrItinData<IIC_LdStSync , [InstrStage<35, [G5_SLU]>]>, 83 InstrItinData<IIC_SprISYNC , [InstrStage<40, [G5_SLU]>]>, // needs work 84 InstrItinData<IIC_SprMFSR , [InstrStage<3, [G5_SLU]>]>, 85 InstrItinData<IIC_SprMTMSR , [InstrStage<3, [G5_SLU]>]>, 86 InstrItinData<IIC_SprMTSR , [InstrStage<3, [G5_SLU]>]>, 87 InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G5_SLU]>]>, 88 InstrItinData<IIC_SprMFCR , [InstrStage<2, [G5_IU2]>]>, 89 InstrItinData<IIC_SprMFCRF , [InstrStage<2, [G5_IU2]>]>, 90 InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G5_IU2]>]>, 91 InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G5_IU2]>]>, 92 InstrItinData<IIC_SprMFTB , [InstrStage<10, [G5_IU2]>]>, 93 InstrItinData<IIC_SprMTSPR , [InstrStage<8, [G5_IU2]>]>, 94 InstrItinData<IIC_SprSC , [InstrStage<1, [G5_IU2]>]>, 95 InstrItinData<IIC_FPGeneral , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, 96 InstrItinData<IIC_FPAddSub , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, 97 InstrItinData<IIC_FPCompare , [InstrStage<8, [G5_FPU1, G5_FPU2]>]>, 98 InstrItinData<IIC_FPDivD , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>, 99 InstrItinData<IIC_FPDivS , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>, 100 InstrItinData<IIC_FPFused , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, 101 InstrItinData<IIC_FPRes , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, 102 InstrItinData<IIC_FPSqrtD , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>, 103 InstrItinData<IIC_FPSqrtS , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>, 104 InstrItinData<IIC_VecGeneral , [InstrStage<2, [G5_VIU1]>]>, 105 InstrItinData<IIC_VecFP , [InstrStage<8, [G5_VFPU]>]>, 106 InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G5_VFPU]>]>, 107 InstrItinData<IIC_VecComplex , [InstrStage<5, [G5_VIU2]>]>, 108 InstrItinData<IIC_VecPerm , [InstrStage<3, [G5_VPU]>]>, 109 InstrItinData<IIC_VecFPRound , [InstrStage<8, [G5_VFPU]>]>, 110 InstrItinData<IIC_VecVSL , [InstrStage<2, [G5_VIU1]>]>, 111 InstrItinData<IIC_VecVSR , [InstrStage<3, [G5_VPU]>]> 112]>; 113 114// ===---------------------------------------------------------------------===// 115// G5 machine model for scheduling and other instruction cost heuristics. 116 117def G5Model : SchedMachineModel { 118 let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle. 119 let LoadLatency = 3; // Optimistic load latency assuming bypass. 120 // This is overriden by OperandCycles if the 121 // Itineraries are queried instead. 122 let MispredictPenalty = 16; 123 124 let CompleteModel = 0; 125 126 let Itineraries = G5Itineraries; 127} 128 129