1 //===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLVM_LIB_TARGET_RISCV_MATINT_H 10 #define LLVM_LIB_TARGET_RISCV_MATINT_H 11 12 #include "llvm/ADT/SmallVector.h" 13 #include <cstdint> 14 15 namespace llvm { 16 class APInt; 17 18 namespace RISCVMatInt { 19 struct Inst { 20 unsigned Opc; 21 int64_t Imm; 22 InstInst23 Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {} 24 }; 25 using InstSeq = SmallVector<Inst, 8>; 26 27 // Helper to generate an instruction sequence that will materialise the given 28 // immediate value into a register. A sequence of instructions represented by 29 // a simple struct produced rather than directly emitting the instructions in 30 // order to allow this helper to be used from both the MC layer and during 31 // instruction selection. 32 void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res); 33 34 // Helper to estimate the number of instructions required to materialise the 35 // given immediate value into a register. This estimate does not account for 36 // `Val` possibly fitting into an immediate, and so may over-estimate. 37 // 38 // This will attempt to produce instructions to materialise `Val` as an 39 // `Size`-bit immediate. `IsRV64` should match the target architecture. 40 int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64); 41 } // namespace RISCVMatInt 42 } // namespace llvm 43 #endif 44