1//===-- XCore.td - Describe the XCore Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the XCore target. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// Descriptions 21//===----------------------------------------------------------------------===// 22 23include "XCoreRegisterInfo.td" 24include "XCoreInstrInfo.td" 25include "XCoreCallingConv.td" 26 27def XCoreInstrInfo : InstrInfo; 28 29//===----------------------------------------------------------------------===// 30// XCore processors supported. 31//===----------------------------------------------------------------------===// 32 33class Proc<string Name, list<SubtargetFeature> Features> 34 : Processor<Name, NoItineraries, Features>; 35 36def : Proc<"generic", []>; 37def : Proc<"xs1b-generic", []>; 38 39//===----------------------------------------------------------------------===// 40// Declare the target which we are implementing 41//===----------------------------------------------------------------------===// 42 43def XCore : Target { 44 // Pull in Instruction Info: 45 let InstructionSet = XCoreInstrInfo; 46} 47