1; RUN: opt -mtriple amdgcn-unknown-amdhsa -analyze -divergence -use-gpu-divergence-analysis %s | FileCheck %s 2 3; CHECK-LABEL: for function 'readfirstlane': 4define amdgpu_kernel void @readfirstlane() { 5 %id.x = call i32 @llvm.amdgcn.workitem.id.x() 6; CHECK: DIVERGENT: %id.x = call i32 @llvm.amdgcn.workitem.id.x() 7 %first.lane = call i32 @llvm.amdgcn.readfirstlane(i32 %id.x) 8; CHECK-NOT: DIVERGENT: %first.lane = call i32 @llvm.amdgcn.readfirstlane(i32 %id.x) 9 ret void 10} 11 12; CHECK-LABEL: for function 'icmp': 13define amdgpu_kernel void @icmp(i32 inreg %x) { 14; CHECK-NOT: DIVERGENT: %icmp = call i64 @llvm.amdgcn.icmp.i32 15 %icmp = call i64 @llvm.amdgcn.icmp.i32(i32 %x, i32 0, i32 33) 16 ret void 17} 18 19; CHECK-LABEL: for function 'fcmp': 20define amdgpu_kernel void @fcmp(float inreg %x, float inreg %y) { 21; CHECK-NOT: DIVERGENT: %fcmp = call i64 @llvm.amdgcn.fcmp.i32 22 %fcmp = call i64 @llvm.amdgcn.fcmp.i32(float %x, float %y, i32 33) 23 ret void 24} 25 26; CHECK-LABEL: for function 'ballot': 27define amdgpu_kernel void @ballot(i1 inreg %x) { 28; CHECK-NOT: DIVERGENT: %ballot = call i64 @llvm.amdgcn.ballot.i32 29 %ballot = call i64 @llvm.amdgcn.ballot.i32(i1 %x) 30 ret void 31} 32 33; SGPR asm outputs are uniform regardless of the input operands. 34; CHECK-LABEL: for function 'asm_sgpr': 35; CHECK: DIVERGENT: i32 %divergent 36; CHECK-NOT: DIVERGENT 37define i32 @asm_sgpr(i32 %divergent) { 38 %sgpr = call i32 asm "; def $0, $1","=s,v"(i32 %divergent) 39 ret i32 %sgpr 40} 41 42; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'asm_mixed_sgpr_vgpr': 43; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1, $2", "=s,=v,v"(i32 %divergent) 44; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 0 45; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 1 46define void @asm_mixed_sgpr_vgpr(i32 %divergent) { 47 %asm = call { i32, i32 } asm "; def $0, $1, $2","=s,=v,v"(i32 %divergent) 48 %sgpr = extractvalue { i32, i32 } %asm, 0 49 %vgpr = extractvalue { i32, i32 } %asm, 1 50 store i32 %sgpr, i32 addrspace(1)* undef 51 store i32 %vgpr, i32 addrspace(1)* undef 52 ret void 53} 54 55declare i32 @llvm.amdgcn.workitem.id.x() #0 56declare i32 @llvm.amdgcn.readfirstlane(i32) #0 57declare i64 @llvm.amdgcn.icmp.i32(i32, i32, i32) #1 58declare i64 @llvm.amdgcn.fcmp.i32(float, float, i32) #1 59declare i64 @llvm.amdgcn.ballot.i32(i1) #1 60 61attributes #0 = { nounwind readnone } 62attributes #1 = { nounwind readnone convergent } 63