1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -mtriple=aarch64-darwin-ios13 -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s 3 4define void @asm_simple_memory_clobber() { 5 ; CHECK-LABEL: name: asm_simple_memory_clobber 6 ; CHECK: bb.1 (%ir-block.0): 7 ; CHECK: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, !0 8 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, !0 9 ; CHECK: RET_ReallyLR 10 call void asm sideeffect "", "~{memory}"(), !srcloc !0 11 call void asm sideeffect "", ""(), !srcloc !0 12 ret void 13} 14 15!0 = !{i32 70} 16 17define void @asm_simple_register_clobber() { 18 ; CHECK-LABEL: name: asm_simple_register_clobber 19 ; CHECK: bb.1 (%ir-block.0): 20 ; CHECK: INLINEASM &"mov x0, 7", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $x0, !0 21 ; CHECK: RET_ReallyLR 22 call void asm sideeffect "mov x0, 7", "~{x0}"(), !srcloc !0 23 ret void 24} 25 26define i64 @asm_register_early_clobber() { 27 ; CHECK-LABEL: name: asm_register_early_clobber 28 ; CHECK: bb.1 (%ir-block.0): 29 ; CHECK: INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, 1441803 /* regdef-ec:GPR64common */, def early-clobber %0, 1441803 /* regdef-ec:GPR64common */, def early-clobber %1, !0 30 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %0 31 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %1 32 ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] 33 ; CHECK: $x0 = COPY [[ADD]](s64) 34 ; CHECK: RET_ReallyLR implicit $x0 35 call { i64, i64 } asm sideeffect "mov $0, 7; mov $1, 7", "=&r,=&r"(), !srcloc !0 36 %asmresult = extractvalue { i64, i64 } %1, 0 37 %asmresult1 = extractvalue { i64, i64 } %1, 1 38 %add = add i64 %asmresult, %asmresult1 39 ret i64 %add 40} 41 42define i32 @test_specific_register_output() nounwind ssp { 43 ; CHECK-LABEL: name: test_specific_register_output 44 ; CHECK: bb.1.entry: 45 ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 10 /* regdef */, implicit-def $w0 46 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 47 ; CHECK: $w0 = COPY [[COPY]](s32) 48 ; CHECK: RET_ReallyLR implicit $w0 49entry: 50 %0 = tail call i32 asm "mov ${0:w}, 7", "={w0}"() nounwind 51 ret i32 %0 52} 53 54define i32 @test_single_register_output() nounwind ssp { 55 ; CHECK-LABEL: name: test_single_register_output 56 ; CHECK: bb.1.entry: 57 ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %0 58 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %0 59 ; CHECK: $w0 = COPY [[COPY]](s32) 60 ; CHECK: RET_ReallyLR implicit $w0 61entry: 62 %0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind 63 ret i32 %0 64} 65 66define i64 @test_single_register_output_s64() nounwind ssp { 67 ; CHECK-LABEL: name: test_single_register_output_s64 68 ; CHECK: bb.1.entry: 69 ; CHECK: INLINEASM &"mov $0, 7", 0 /* attdialect */, 1441802 /* regdef:GPR64common */, def %0 70 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %0 71 ; CHECK: $x0 = COPY [[COPY]](s64) 72 ; CHECK: RET_ReallyLR implicit $x0 73entry: 74 %0 = tail call i64 asm "mov $0, 7", "=r"() nounwind 75 ret i64 %0 76} 77 78; Check support for returning several floats 79define float @test_multiple_register_outputs_same() #0 { 80 ; CHECK-LABEL: name: test_multiple_register_outputs_same 81 ; CHECK: bb.1 (%ir-block.0): 82 ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %0, 655370 /* regdef:GPR32common */, def %1 83 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %0 84 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %1 85 ; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]] 86 ; CHECK: $s0 = COPY [[FADD]](s32) 87 ; CHECK: RET_ReallyLR implicit $s0 88 %1 = call { float, float } asm "mov $0, #0; mov $1, #0", "=r,=r"() 89 %asmresult = extractvalue { float, float } %1, 0 90 %asmresult1 = extractvalue { float, float } %1, 1 91 %add = fadd float %asmresult, %asmresult1 92 ret float %add 93} 94 95; Check support for returning several floats 96define double @test_multiple_register_outputs_mixed() #0 { 97 ; CHECK-LABEL: name: test_multiple_register_outputs_mixed 98 ; CHECK: bb.1 (%ir-block.0): 99 ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %0, 1245194 /* regdef:FPR64 */, def %1 100 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %0 101 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %1 102 ; CHECK: $d0 = COPY [[COPY1]](s64) 103 ; CHECK: RET_ReallyLR implicit $d0 104 %1 = call { float, double } asm "mov $0, #0; mov $1, #0", "=r,=w"() 105 %asmresult = extractvalue { float, double } %1, 1 106 ret double %asmresult 107} 108 109define i32 @test_specific_register_output_trunc() nounwind ssp { 110 ; CHECK-LABEL: name: test_specific_register_output_trunc 111 ; CHECK: bb.1.entry: 112 ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 10 /* regdef */, implicit-def $x0 113 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 114 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 115 ; CHECK: $w0 = COPY [[TRUNC]](s32) 116 ; CHECK: RET_ReallyLR implicit $w0 117entry: 118 %0 = tail call i32 asm "mov ${0:w}, 7", "={x0}"() nounwind 119 ret i32 %0 120} 121 122define zeroext i8 @test_register_output_trunc(i8* %src) nounwind { 123 ; CHECK-LABEL: name: test_register_output_trunc 124 ; CHECK: bb.1.entry: 125 ; CHECK: liveins: $x0 126 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 127 ; CHECK: INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %1 128 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %1 129 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) 130 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8) 131 ; CHECK: $w0 = COPY [[ZEXT]](s32) 132 ; CHECK: RET_ReallyLR implicit $w0 133entry: 134 %0 = tail call i8 asm "mov ${0:w}, 32", "=r"() nounwind 135 ret i8 %0 136} 137 138define float @test_vector_output() nounwind { 139 ; CHECK-LABEL: name: test_vector_output 140 ; CHECK: bb.1 (%ir-block.0): 141 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 142 ; CHECK: INLINEASM &"fmov ${0}.2s, #1.0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $d14 143 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d14 144 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s64) 145 ; CHECK: $s0 = COPY [[EVEC]](s32) 146 ; CHECK: RET_ReallyLR implicit $s0 147 %1 = tail call <2 x float> asm sideeffect "fmov ${0}.2s, #1.0", "={v14}"() nounwind 148 %2 = extractelement <2 x float> %1, i32 0 149 ret float %2 150} 151 152define void @test_input_register_imm() { 153 ; CHECK-LABEL: name: test_input_register_imm 154 ; CHECK: bb.1 (%ir-block.0): 155 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42 156 ; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](s64) 157 ; CHECK: INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 1441801 /* reguse:GPR64common */, [[COPY]] 158 ; CHECK: RET_ReallyLR 159 call void asm sideeffect "mov x0, $0", "r"(i64 42) 160 ret void 161} 162 163; Make sure that boolean immediates are properly (zero) extended. 164define i32 @test_boolean_imm_ext() { 165 ; CHECK-LABEL: name: test_boolean_imm_ext 166 ; CHECK: bb.1.entry: 167 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 168 ; CHECK: INLINEASM &"#TEST 42 + ${0:c} - .\0A\09", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 1 169 ; CHECK: $w0 = COPY [[C]](s32) 170 ; CHECK: RET_ReallyLR implicit $w0 171entry: 172 tail call void asm sideeffect "#TEST 42 + ${0:c} - .\0A\09", "i"(i1 true) 173 ret i32 1 174} 175 176define void @test_input_imm() { 177 ; CHECK-LABEL: name: test_input_imm 178 ; CHECK: bb.1 (%ir-block.0): 179 ; CHECK: INLINEASM &"mov x0, $0", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42 180 ; CHECK: RET_ReallyLR 181 call void asm sideeffect "mov x0, $0", "i"(i64 42) 182 ret void 183} 184 185define zeroext i8 @test_input_register(i8* %src) nounwind { 186 ; CHECK-LABEL: name: test_input_register 187 ; CHECK: bb.1.entry: 188 ; CHECK: liveins: $x0 189 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 190 ; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]](p0) 191 ; CHECK: INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %1, 1441801 /* reguse:GPR64common */, [[COPY1]] 192 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY %1 193 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32) 194 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8) 195 ; CHECK: $w0 = COPY [[ZEXT]](s32) 196 ; CHECK: RET_ReallyLR implicit $w0 197entry: 198 %0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(i8* %src) nounwind 199 ret i8 %0 200} 201 202define i32 @test_memory_constraint(i32* %a) nounwind { 203 ; CHECK-LABEL: name: test_memory_constraint 204 ; CHECK: bb.1 (%ir-block.0): 205 ; CHECK: liveins: $x0 206 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 207 ; CHECK: INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, 655370 /* regdef:GPR32common */, def %1, 196622 /* mem:m */, [[COPY]](p0) 208 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %1 209 ; CHECK: $w0 = COPY [[COPY1]](s32) 210 ; CHECK: RET_ReallyLR implicit $w0 211 %1 = tail call i32 asm "ldr $0, $1", "=r,*m"(i32* %a) 212 ret i32 %1 213} 214 215define i16 @test_anyext_input() { 216 ; CHECK-LABEL: name: test_anyext_input 217 ; CHECK: bb.1 (%ir-block.0): 218 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1 219 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16) 220 ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32) 221 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 655370 /* regdef:GPR32common */, def %0, 655369 /* reguse:GPR32common */, [[COPY]] 222 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %0 223 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 224 ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) 225 ; CHECK: $w0 = COPY [[ANYEXT1]](s32) 226 ; CHECK: RET_ReallyLR implicit $w0 227 %1 = call i16 asm sideeffect "", "=r,r"(i16 1) 228 ret i16 %1 229} 230 231define i16 @test_anyext_input_with_matching_constraint() { 232 ; CHECK-LABEL: name: test_anyext_input_with_matching_constraint 233 ; CHECK: bb.1 (%ir-block.0): 234 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1 235 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16) 236 ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32) 237 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 655370 /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3) 238 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %0 239 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 240 ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) 241 ; CHECK: $w0 = COPY [[ANYEXT1]](s32) 242 ; CHECK: RET_ReallyLR implicit $w0 243 %1 = call i16 asm sideeffect "", "=r,0"(i16 1) 244 ret i16 %1 245} 246 247define i64 @test_input_with_matching_constraint_to_physical_register() { 248 ; CHECK-LABEL: name: test_input_with_matching_constraint_to_physical_register 249 ; CHECK: bb.1 (%ir-block.0): 250 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 251 ; CHECK: INLINEASM &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $x2, 2147483657 /* reguse tiedto:$0 */, [[C]](tied-def 3)(s64) 252 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x2 253 ; CHECK: $x0 = COPY [[COPY]](s64) 254 ; CHECK: RET_ReallyLR implicit $x0 255 %1 = tail call i64 asm "", "={x2},0"(i64 0) 256 ret i64 %1 257} 258