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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
3---
4name:            test_div
5body:             |
6  bb.0.entry:
7    ; CHECK-LABEL: name: test_div
8    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
9    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
10    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
11    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
12    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
13    ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
14    ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
15    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
16    ; CHECK: $w0 = COPY [[COPY2]](s32)
17    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
18    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
19    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
20    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
21    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C]]
22    ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
23    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
24    ; CHECK: $w0 = COPY [[COPY3]](s32)
25    %0:_(s64) = COPY $x0
26    %1:_(s64) = COPY $x1
27    %2:_(s8) = G_TRUNC %0(s64)
28    %3:_(s8) = G_TRUNC %1(s64)
29    %4:_(s8) = G_SDIV %2, %3
30    %6:_(s32) = G_ANYEXT %4(s8)
31    $w0 = COPY %6(s32)
32    %5:_(s8) = G_UDIV %2, %3
33    %7:_(s32) = G_ANYEXT %5(s8)
34    $w0 = COPY %7(s32)
35
36...
37---
38name:            sdiv_v4s32
39alignment:       4
40tracksRegLiveness: true
41machineFunctionInfo: {}
42body:             |
43  bb.1:
44    liveins: $q0, $q1
45
46    ; CHECK-LABEL: name: sdiv_v4s32
47    ; CHECK: liveins: $q0, $q1
48    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
49    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
50    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
51    ; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
52    ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[UV]], [[UV4]]
53    ; CHECK: [[SDIV1:%[0-9]+]]:_(s32) = G_SDIV [[UV1]], [[UV5]]
54    ; CHECK: [[SDIV2:%[0-9]+]]:_(s32) = G_SDIV [[UV2]], [[UV6]]
55    ; CHECK: [[SDIV3:%[0-9]+]]:_(s32) = G_SDIV [[UV3]], [[UV7]]
56    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SDIV]](s32), [[SDIV1]](s32), [[SDIV2]](s32), [[SDIV3]](s32)
57    ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)
58    ; CHECK: RET_ReallyLR implicit $q0
59    %0:_(<4 x s32>) = COPY $q0
60    %1:_(<4 x s32>) = COPY $q1
61    %2:_(<4 x s32>) = G_SDIV %0, %1
62    $q0 = COPY %2(<4 x s32>)
63    RET_ReallyLR implicit $q0
64
65...
66