1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s 3--- | 4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 5 target triple = "aarch64" 6 7 define i32 @load_store_test(i24* %ptr, i24* %ptr2) { 8 %val = load i24, i24* %ptr 9 store i24 %val, i24* %ptr2 10 ret i32 0 11 } 12 13... 14--- 15name: load_store_test 16alignment: 4 17tracksRegLiveness: true 18body: | 19 bb.1 (%ir-block.0): 20 liveins: $x0, $x1 21 22 ; CHECK-LABEL: name: load_store_test 23 ; CHECK: liveins: $x0, $x1 24 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 25 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 26 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 27 ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.ptr, align 4) 28 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 29 ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64) 30 ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 1 from %ir.ptr + 2, align 4) 31 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 32 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C2]](s64) 33 ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] 34 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32) 35 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C2]](s64) 36 ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64) 37 ; CHECK: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store 2 into %ir.ptr2, align 4) 38 ; CHECK: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p0) :: (store 1 into %ir.ptr2 + 2, align 4) 39 ; CHECK: $w0 = COPY [[C]](s32) 40 ; CHECK: RET_ReallyLR implicit $w0 41 %0:_(p0) = COPY $x0 42 %1:_(p0) = COPY $x1 43 %3:_(s32) = G_CONSTANT i32 0 44 %2:_(s24) = G_LOAD %0(p0) :: (load 3 from %ir.ptr, align 4) 45 G_STORE %2(s24), %1(p0) :: (store 3 into %ir.ptr2, align 4) 46 $w0 = COPY %3(s32) 47 RET_ReallyLR implicit $w0 48 49... 50