1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -O0 -march=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s 3--- 4name: add_v16s8 5tracksRegLiveness: true 6body: | 7 bb.1: 8 liveins: $x0 9 10 ; CHECK-LABEL: name: add_v16s8 11 ; CHECK: liveins: $x0 12 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 13 ; CHECK: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16) 14 ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s8) = G_VECREDUCE_ADD [[LOAD]](<16 x s8>) 15 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s8) 16 ; CHECK: $w0 = COPY [[ANYEXT]](s32) 17 ; CHECK: RET_ReallyLR implicit $w0 18 %0:_(p0) = COPY $x0 19 %1:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16) 20 %2:_(s8) = G_VECREDUCE_ADD %1(<16 x s8>) 21 %3:_(s32) = G_ANYEXT %2(s8) 22 $w0 = COPY %3(s32) 23 RET_ReallyLR implicit $w0 24 25... 26--- 27name: add_v8s16 28tracksRegLiveness: true 29body: | 30 bb.1: 31 liveins: $x0 32 33 ; CHECK-LABEL: name: add_v8s16 34 ; CHECK: liveins: $x0 35 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 36 ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16) 37 ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s16) = G_VECREDUCE_ADD [[LOAD]](<8 x s16>) 38 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s16) 39 ; CHECK: $w0 = COPY [[ANYEXT]](s32) 40 ; CHECK: RET_ReallyLR implicit $w0 41 %0:_(p0) = COPY $x0 42 %1:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16) 43 %2:_(s16) = G_VECREDUCE_ADD %1(<8 x s16>) 44 %3:_(s32) = G_ANYEXT %2(s16) 45 $w0 = COPY %3(s32) 46 RET_ReallyLR implicit $w0 47 48... 49--- 50name: add_v4s32 51tracksRegLiveness: true 52body: | 53 bb.1: 54 liveins: $x0 55 56 ; CHECK-LABEL: name: add_v4s32 57 ; CHECK: liveins: $x0 58 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 59 ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16) 60 ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<4 x s32>) 61 ; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32) 62 ; CHECK: RET_ReallyLR implicit $w0 63 %0:_(p0) = COPY $x0 64 %1:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16) 65 %2:_(s32) = G_VECREDUCE_ADD %1(<4 x s32>) 66 $w0 = COPY %2(s32) 67 RET_ReallyLR implicit $w0 68 69... 70--- 71name: add_v2s64 72tracksRegLiveness: true 73body: | 74 bb.1: 75 liveins: $x0 76 77 ; CHECK-LABEL: name: add_v2s64 78 ; CHECK: liveins: $x0 79 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 80 ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16) 81 ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[LOAD]](<2 x s64>) 82 ; CHECK: $x0 = COPY [[VECREDUCE_ADD]](s64) 83 ; CHECK: RET_ReallyLR implicit $x0 84 %0:_(p0) = COPY $x0 85 %1:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16) 86 %2:_(s64) = G_VECREDUCE_ADD %1(<2 x s64>) 87 $x0 = COPY %2(s64) 88 RET_ReallyLR implicit $x0 89 90... 91