1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s 3--- 4name: test_v2i64_eq 5alignment: 4 6tracksRegLiveness: true 7registers: 8 - { id: 0, class: _ } 9 - { id: 1, class: _ } 10 - { id: 2, class: _ } 11 - { id: 3, class: _ } 12machineFunctionInfo: {} 13body: | 14 bb.1: 15 liveins: $q0, $q1 16 17 ; CHECK-LABEL: name: test_v2i64_eq 18 ; CHECK: liveins: $q0, $q1 19 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 20 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 21 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[COPY]](<2 x s64>), [[COPY1]] 22 ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 23 ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>) 24 ; CHECK: RET_ReallyLR implicit $d0 25 %0:_(<2 x s64>) = COPY $q0 26 %1:_(<2 x s64>) = COPY $q1 27 %2:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s64>), %1 28 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 29 $d0 = COPY %3(<2 x s32>) 30 RET_ReallyLR implicit $d0 31 32... 33--- 34name: test_v4i32_eq 35alignment: 4 36tracksRegLiveness: true 37registers: 38 - { id: 0, class: _ } 39 - { id: 1, class: _ } 40 - { id: 2, class: _ } 41 - { id: 3, class: _ } 42machineFunctionInfo: {} 43body: | 44 bb.1: 45 liveins: $q0, $q1 46 47 ; CHECK-LABEL: name: test_v4i32_eq 48 ; CHECK: liveins: $q0, $q1 49 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 50 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 51 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY1]] 52 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 53 ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>) 54 ; CHECK: RET_ReallyLR implicit $d0 55 %0:_(<4 x s32>) = COPY $q0 56 %1:_(<4 x s32>) = COPY $q1 57 %2:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s32>), %1 58 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 59 $d0 = COPY %3(<4 x s16>) 60 RET_ReallyLR implicit $d0 61 62... 63--- 64name: test_v2i32_eq 65alignment: 4 66tracksRegLiveness: true 67registers: 68 - { id: 0, class: _ } 69 - { id: 1, class: _ } 70 - { id: 2, class: _ } 71 - { id: 3, class: _ } 72machineFunctionInfo: {} 73body: | 74 bb.1: 75 liveins: $d0, $d1 76 77 ; CHECK-LABEL: name: test_v2i32_eq 78 ; CHECK: liveins: $d0, $d1 79 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 80 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 81 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]] 82 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>) 83 ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>) 84 ; CHECK: RET_ReallyLR implicit $d0 85 %0:_(<2 x s32>) = COPY $d0 86 %1:_(<2 x s32>) = COPY $d1 87 %2:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1 88 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 89 $d0 = COPY %3(<2 x s32>) 90 RET_ReallyLR implicit $d0 91 92... 93--- 94name: test_v8i16_eq 95alignment: 4 96tracksRegLiveness: true 97registers: 98 - { id: 0, class: _ } 99 - { id: 1, class: _ } 100 - { id: 2, class: _ } 101 - { id: 3, class: _ } 102machineFunctionInfo: {} 103body: | 104 bb.1: 105 liveins: $q0, $q1 106 107 ; CHECK-LABEL: name: test_v8i16_eq 108 ; CHECK: liveins: $q0, $q1 109 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 110 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 111 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(eq), [[COPY]](<8 x s16>), [[COPY1]] 112 ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 113 ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>) 114 ; CHECK: RET_ReallyLR implicit $d0 115 %0:_(<8 x s16>) = COPY $q0 116 %1:_(<8 x s16>) = COPY $q1 117 %2:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s16>), %1 118 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 119 $d0 = COPY %3(<8 x s8>) 120 RET_ReallyLR implicit $d0 121 122... 123--- 124name: test_v4i16_eq 125alignment: 4 126tracksRegLiveness: true 127registers: 128 - { id: 0, class: _ } 129 - { id: 1, class: _ } 130 - { id: 2, class: _ } 131 - { id: 3, class: _ } 132machineFunctionInfo: {} 133body: | 134 bb.1: 135 liveins: $d0, $d1 136 137 ; CHECK-LABEL: name: test_v4i16_eq 138 ; CHECK: liveins: $d0, $d1 139 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 140 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 141 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]] 142 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>) 143 ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>) 144 ; CHECK: RET_ReallyLR implicit $d0 145 %0:_(<4 x s16>) = COPY $d0 146 %1:_(<4 x s16>) = COPY $d1 147 %2:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1 148 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 149 $d0 = COPY %3(<4 x s16>) 150 RET_ReallyLR implicit $d0 151 152... 153--- 154name: test_v16i8_eq 155alignment: 4 156tracksRegLiveness: true 157registers: 158 - { id: 0, class: _ } 159 - { id: 1, class: _ } 160 - { id: 2, class: _ } 161 - { id: 3, class: _ } 162machineFunctionInfo: {} 163body: | 164 bb.1: 165 liveins: $q0, $q1 166 167 ; CHECK-LABEL: name: test_v16i8_eq 168 ; CHECK: liveins: $q0, $q1 169 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 170 ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 171 ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]] 172 ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>) 173 ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>) 174 ; CHECK: RET_ReallyLR implicit $q0 175 %0:_(<16 x s8>) = COPY $q0 176 %1:_(<16 x s8>) = COPY $q1 177 %2:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1 178 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 179 $q0 = COPY %3(<16 x s8>) 180 RET_ReallyLR implicit $q0 181 182... 183--- 184name: test_v8i8_eq 185alignment: 4 186tracksRegLiveness: true 187registers: 188 - { id: 0, class: _ } 189 - { id: 1, class: _ } 190 - { id: 2, class: _ } 191 - { id: 3, class: _ } 192machineFunctionInfo: {} 193body: | 194 bb.1: 195 liveins: $d0, $d1 196 197 ; CHECK-LABEL: name: test_v8i8_eq 198 ; CHECK: liveins: $d0, $d1 199 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 200 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 201 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]] 202 ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>) 203 ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>) 204 ; CHECK: RET_ReallyLR implicit $d0 205 %0:_(<8 x s8>) = COPY $d0 206 %1:_(<8 x s8>) = COPY $d1 207 %2:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1 208 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 209 $d0 = COPY %3(<8 x s8>) 210 RET_ReallyLR implicit $d0 211 212... 213--- 214name: test_v2i64_ugt 215alignment: 4 216tracksRegLiveness: true 217registers: 218 - { id: 0, class: _ } 219 - { id: 1, class: _ } 220 - { id: 2, class: _ } 221 - { id: 3, class: _ } 222machineFunctionInfo: {} 223body: | 224 bb.1: 225 liveins: $q0, $q1 226 227 ; CHECK-LABEL: name: test_v2i64_ugt 228 ; CHECK: liveins: $q0, $q1 229 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 230 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 231 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[COPY]](<2 x s64>), [[COPY1]] 232 ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 233 ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>) 234 ; CHECK: RET_ReallyLR implicit $d0 235 %0:_(<2 x s64>) = COPY $q0 236 %1:_(<2 x s64>) = COPY $q1 237 %2:_(<2 x s1>) = G_ICMP intpred(ugt), %0(<2 x s64>), %1 238 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 239 $d0 = COPY %3(<2 x s32>) 240 RET_ReallyLR implicit $d0 241 242... 243--- 244name: test_v4i32_ugt 245alignment: 4 246tracksRegLiveness: true 247registers: 248 - { id: 0, class: _ } 249 - { id: 1, class: _ } 250 - { id: 2, class: _ } 251 - { id: 3, class: _ } 252machineFunctionInfo: {} 253body: | 254 bb.1: 255 liveins: $q0, $q1 256 257 ; CHECK-LABEL: name: test_v4i32_ugt 258 ; CHECK: liveins: $q0, $q1 259 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 260 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 261 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ugt), [[COPY]](<4 x s32>), [[COPY1]] 262 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 263 ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>) 264 ; CHECK: RET_ReallyLR implicit $d0 265 %0:_(<4 x s32>) = COPY $q0 266 %1:_(<4 x s32>) = COPY $q1 267 %2:_(<4 x s1>) = G_ICMP intpred(ugt), %0(<4 x s32>), %1 268 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 269 $d0 = COPY %3(<4 x s16>) 270 RET_ReallyLR implicit $d0 271 272... 273--- 274name: test_v2i32_ugt 275alignment: 4 276tracksRegLiveness: true 277registers: 278 - { id: 0, class: _ } 279 - { id: 1, class: _ } 280 - { id: 2, class: _ } 281 - { id: 3, class: _ } 282machineFunctionInfo: {} 283body: | 284 bb.1: 285 liveins: $d0, $d1 286 287 ; CHECK-LABEL: name: test_v2i32_ugt 288 ; CHECK: liveins: $d0, $d1 289 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 290 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 291 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ugt), [[COPY]](<2 x s32>), [[COPY1]] 292 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>) 293 ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>) 294 ; CHECK: RET_ReallyLR implicit $d0 295 %0:_(<2 x s32>) = COPY $d0 296 %1:_(<2 x s32>) = COPY $d1 297 %2:_(<2 x s1>) = G_ICMP intpred(ugt), %0(<2 x s32>), %1 298 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 299 $d0 = COPY %3(<2 x s32>) 300 RET_ReallyLR implicit $d0 301 302... 303--- 304name: test_v8i16_ugt 305alignment: 4 306tracksRegLiveness: true 307registers: 308 - { id: 0, class: _ } 309 - { id: 1, class: _ } 310 - { id: 2, class: _ } 311 - { id: 3, class: _ } 312machineFunctionInfo: {} 313body: | 314 bb.1: 315 liveins: $q0, $q1 316 317 ; CHECK-LABEL: name: test_v8i16_ugt 318 ; CHECK: liveins: $q0, $q1 319 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 320 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 321 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(ugt), [[COPY]](<8 x s16>), [[COPY1]] 322 ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 323 ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>) 324 ; CHECK: RET_ReallyLR implicit $d0 325 %0:_(<8 x s16>) = COPY $q0 326 %1:_(<8 x s16>) = COPY $q1 327 %2:_(<8 x s1>) = G_ICMP intpred(ugt), %0(<8 x s16>), %1 328 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 329 $d0 = COPY %3(<8 x s8>) 330 RET_ReallyLR implicit $d0 331 332... 333--- 334name: test_v4i16_ugt 335alignment: 4 336tracksRegLiveness: true 337registers: 338 - { id: 0, class: _ } 339 - { id: 1, class: _ } 340 - { id: 2, class: _ } 341 - { id: 3, class: _ } 342machineFunctionInfo: {} 343body: | 344 bb.1: 345 liveins: $d0, $d1 346 347 ; CHECK-LABEL: name: test_v4i16_ugt 348 ; CHECK: liveins: $d0, $d1 349 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 350 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 351 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ugt), [[COPY]](<4 x s16>), [[COPY1]] 352 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>) 353 ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>) 354 ; CHECK: RET_ReallyLR implicit $d0 355 %0:_(<4 x s16>) = COPY $d0 356 %1:_(<4 x s16>) = COPY $d1 357 %2:_(<4 x s1>) = G_ICMP intpred(ugt), %0(<4 x s16>), %1 358 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 359 $d0 = COPY %3(<4 x s16>) 360 RET_ReallyLR implicit $d0 361 362... 363--- 364name: test_v16i8_ugt 365alignment: 4 366tracksRegLiveness: true 367registers: 368 - { id: 0, class: _ } 369 - { id: 1, class: _ } 370 - { id: 2, class: _ } 371 - { id: 3, class: _ } 372machineFunctionInfo: {} 373body: | 374 bb.1: 375 liveins: $q0, $q1 376 377 ; CHECK-LABEL: name: test_v16i8_ugt 378 ; CHECK: liveins: $q0, $q1 379 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 380 ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 381 ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ugt), [[COPY]](<16 x s8>), [[COPY1]] 382 ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>) 383 ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>) 384 ; CHECK: RET_ReallyLR implicit $q0 385 %0:_(<16 x s8>) = COPY $q0 386 %1:_(<16 x s8>) = COPY $q1 387 %2:_(<16 x s1>) = G_ICMP intpred(ugt), %0(<16 x s8>), %1 388 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 389 $q0 = COPY %3(<16 x s8>) 390 RET_ReallyLR implicit $q0 391 392... 393--- 394name: test_v8i8_ugt 395alignment: 4 396tracksRegLiveness: true 397registers: 398 - { id: 0, class: _ } 399 - { id: 1, class: _ } 400 - { id: 2, class: _ } 401 - { id: 3, class: _ } 402machineFunctionInfo: {} 403body: | 404 bb.1: 405 liveins: $d0, $d1 406 407 ; CHECK-LABEL: name: test_v8i8_ugt 408 ; CHECK: liveins: $d0, $d1 409 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 410 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 411 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ugt), [[COPY]](<8 x s8>), [[COPY1]] 412 ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>) 413 ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>) 414 ; CHECK: RET_ReallyLR implicit $d0 415 %0:_(<8 x s8>) = COPY $d0 416 %1:_(<8 x s8>) = COPY $d1 417 %2:_(<8 x s1>) = G_ICMP intpred(ugt), %0(<8 x s8>), %1 418 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 419 $d0 = COPY %3(<8 x s8>) 420 RET_ReallyLR implicit $d0 421 422... 423--- 424name: test_v2i64_uge 425alignment: 4 426tracksRegLiveness: true 427registers: 428 - { id: 0, class: _ } 429 - { id: 1, class: _ } 430 - { id: 2, class: _ } 431 - { id: 3, class: _ } 432machineFunctionInfo: {} 433body: | 434 bb.1: 435 liveins: $q0, $q1 436 437 ; CHECK-LABEL: name: test_v2i64_uge 438 ; CHECK: liveins: $q0, $q1 439 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 440 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 441 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(uge), [[COPY]](<2 x s64>), [[COPY1]] 442 ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 443 ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>) 444 ; CHECK: RET_ReallyLR implicit $d0 445 %0:_(<2 x s64>) = COPY $q0 446 %1:_(<2 x s64>) = COPY $q1 447 %2:_(<2 x s1>) = G_ICMP intpred(uge), %0(<2 x s64>), %1 448 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 449 $d0 = COPY %3(<2 x s32>) 450 RET_ReallyLR implicit $d0 451 452... 453--- 454name: test_v4i32_uge 455alignment: 4 456tracksRegLiveness: true 457registers: 458 - { id: 0, class: _ } 459 - { id: 1, class: _ } 460 - { id: 2, class: _ } 461 - { id: 3, class: _ } 462machineFunctionInfo: {} 463body: | 464 bb.1: 465 liveins: $q0, $q1 466 467 ; CHECK-LABEL: name: test_v4i32_uge 468 ; CHECK: liveins: $q0, $q1 469 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 470 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 471 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(uge), [[COPY]](<4 x s32>), [[COPY1]] 472 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 473 ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>) 474 ; CHECK: RET_ReallyLR implicit $d0 475 %0:_(<4 x s32>) = COPY $q0 476 %1:_(<4 x s32>) = COPY $q1 477 %2:_(<4 x s1>) = G_ICMP intpred(uge), %0(<4 x s32>), %1 478 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 479 $d0 = COPY %3(<4 x s16>) 480 RET_ReallyLR implicit $d0 481 482... 483--- 484name: test_v2i32_uge 485alignment: 4 486tracksRegLiveness: true 487registers: 488 - { id: 0, class: _ } 489 - { id: 1, class: _ } 490 - { id: 2, class: _ } 491 - { id: 3, class: _ } 492machineFunctionInfo: {} 493body: | 494 bb.1: 495 liveins: $d0, $d1 496 497 ; CHECK-LABEL: name: test_v2i32_uge 498 ; CHECK: liveins: $d0, $d1 499 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 500 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 501 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(uge), [[COPY]](<2 x s32>), [[COPY1]] 502 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>) 503 ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>) 504 ; CHECK: RET_ReallyLR implicit $d0 505 %0:_(<2 x s32>) = COPY $d0 506 %1:_(<2 x s32>) = COPY $d1 507 %2:_(<2 x s1>) = G_ICMP intpred(uge), %0(<2 x s32>), %1 508 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 509 $d0 = COPY %3(<2 x s32>) 510 RET_ReallyLR implicit $d0 511 512... 513--- 514name: test_v8i16_uge 515alignment: 4 516tracksRegLiveness: true 517registers: 518 - { id: 0, class: _ } 519 - { id: 1, class: _ } 520 - { id: 2, class: _ } 521 - { id: 3, class: _ } 522machineFunctionInfo: {} 523body: | 524 bb.1: 525 liveins: $q0, $q1 526 527 ; CHECK-LABEL: name: test_v8i16_uge 528 ; CHECK: liveins: $q0, $q1 529 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 530 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 531 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(uge), [[COPY]](<8 x s16>), [[COPY1]] 532 ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 533 ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>) 534 ; CHECK: RET_ReallyLR implicit $d0 535 %0:_(<8 x s16>) = COPY $q0 536 %1:_(<8 x s16>) = COPY $q1 537 %2:_(<8 x s1>) = G_ICMP intpred(uge), %0(<8 x s16>), %1 538 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 539 $d0 = COPY %3(<8 x s8>) 540 RET_ReallyLR implicit $d0 541 542... 543--- 544name: test_v4i16_uge 545alignment: 4 546tracksRegLiveness: true 547registers: 548 - { id: 0, class: _ } 549 - { id: 1, class: _ } 550 - { id: 2, class: _ } 551 - { id: 3, class: _ } 552machineFunctionInfo: {} 553body: | 554 bb.1: 555 liveins: $d0, $d1 556 557 ; CHECK-LABEL: name: test_v4i16_uge 558 ; CHECK: liveins: $d0, $d1 559 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 560 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 561 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(uge), [[COPY]](<4 x s16>), [[COPY1]] 562 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>) 563 ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>) 564 ; CHECK: RET_ReallyLR implicit $d0 565 %0:_(<4 x s16>) = COPY $d0 566 %1:_(<4 x s16>) = COPY $d1 567 %2:_(<4 x s1>) = G_ICMP intpred(uge), %0(<4 x s16>), %1 568 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 569 $d0 = COPY %3(<4 x s16>) 570 RET_ReallyLR implicit $d0 571 572... 573--- 574name: test_v16i8_uge 575alignment: 4 576tracksRegLiveness: true 577registers: 578 - { id: 0, class: _ } 579 - { id: 1, class: _ } 580 - { id: 2, class: _ } 581 - { id: 3, class: _ } 582machineFunctionInfo: {} 583body: | 584 bb.1: 585 liveins: $q0, $q1 586 587 ; CHECK-LABEL: name: test_v16i8_uge 588 ; CHECK: liveins: $q0, $q1 589 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 590 ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 591 ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(uge), [[COPY]](<16 x s8>), [[COPY1]] 592 ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>) 593 ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>) 594 ; CHECK: RET_ReallyLR implicit $q0 595 %0:_(<16 x s8>) = COPY $q0 596 %1:_(<16 x s8>) = COPY $q1 597 %2:_(<16 x s1>) = G_ICMP intpred(uge), %0(<16 x s8>), %1 598 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 599 $q0 = COPY %3(<16 x s8>) 600 RET_ReallyLR implicit $q0 601 602... 603--- 604name: test_v8i8_uge 605alignment: 4 606tracksRegLiveness: true 607registers: 608 - { id: 0, class: _ } 609 - { id: 1, class: _ } 610 - { id: 2, class: _ } 611 - { id: 3, class: _ } 612machineFunctionInfo: {} 613body: | 614 bb.1: 615 liveins: $d0, $d1 616 617 ; CHECK-LABEL: name: test_v8i8_uge 618 ; CHECK: liveins: $d0, $d1 619 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 620 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 621 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(uge), [[COPY]](<8 x s8>), [[COPY1]] 622 ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>) 623 ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>) 624 ; CHECK: RET_ReallyLR implicit $d0 625 %0:_(<8 x s8>) = COPY $d0 626 %1:_(<8 x s8>) = COPY $d1 627 %2:_(<8 x s1>) = G_ICMP intpred(uge), %0(<8 x s8>), %1 628 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 629 $d0 = COPY %3(<8 x s8>) 630 RET_ReallyLR implicit $d0 631 632... 633--- 634name: test_v2i64_ult 635alignment: 4 636tracksRegLiveness: true 637registers: 638 - { id: 0, class: _ } 639 - { id: 1, class: _ } 640 - { id: 2, class: _ } 641 - { id: 3, class: _ } 642machineFunctionInfo: {} 643body: | 644 bb.1: 645 liveins: $q0, $q1 646 647 ; CHECK-LABEL: name: test_v2i64_ult 648 ; CHECK: liveins: $q0, $q1 649 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 650 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 651 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[COPY]](<2 x s64>), [[COPY1]] 652 ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 653 ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>) 654 ; CHECK: RET_ReallyLR implicit $d0 655 %0:_(<2 x s64>) = COPY $q0 656 %1:_(<2 x s64>) = COPY $q1 657 %2:_(<2 x s1>) = G_ICMP intpred(ult), %0(<2 x s64>), %1 658 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 659 $d0 = COPY %3(<2 x s32>) 660 RET_ReallyLR implicit $d0 661 662... 663--- 664name: test_v4i32_ult 665alignment: 4 666tracksRegLiveness: true 667registers: 668 - { id: 0, class: _ } 669 - { id: 1, class: _ } 670 - { id: 2, class: _ } 671 - { id: 3, class: _ } 672machineFunctionInfo: {} 673body: | 674 bb.1: 675 liveins: $q0, $q1 676 677 ; CHECK-LABEL: name: test_v4i32_ult 678 ; CHECK: liveins: $q0, $q1 679 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 680 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 681 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ult), [[COPY]](<4 x s32>), [[COPY1]] 682 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 683 ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>) 684 ; CHECK: RET_ReallyLR implicit $d0 685 %0:_(<4 x s32>) = COPY $q0 686 %1:_(<4 x s32>) = COPY $q1 687 %2:_(<4 x s1>) = G_ICMP intpred(ult), %0(<4 x s32>), %1 688 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 689 $d0 = COPY %3(<4 x s16>) 690 RET_ReallyLR implicit $d0 691 692... 693--- 694name: test_v2i32_ult 695alignment: 4 696tracksRegLiveness: true 697registers: 698 - { id: 0, class: _ } 699 - { id: 1, class: _ } 700 - { id: 2, class: _ } 701 - { id: 3, class: _ } 702machineFunctionInfo: {} 703body: | 704 bb.1: 705 liveins: $d0, $d1 706 707 ; CHECK-LABEL: name: test_v2i32_ult 708 ; CHECK: liveins: $d0, $d1 709 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 710 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 711 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]] 712 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>) 713 ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>) 714 ; CHECK: RET_ReallyLR implicit $d0 715 %0:_(<2 x s32>) = COPY $d0 716 %1:_(<2 x s32>) = COPY $d1 717 %2:_(<2 x s1>) = G_ICMP intpred(ult), %0(<2 x s32>), %1 718 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 719 $d0 = COPY %3(<2 x s32>) 720 RET_ReallyLR implicit $d0 721 722... 723--- 724name: test_v8i16_ult 725alignment: 4 726tracksRegLiveness: true 727registers: 728 - { id: 0, class: _ } 729 - { id: 1, class: _ } 730 - { id: 2, class: _ } 731 - { id: 3, class: _ } 732machineFunctionInfo: {} 733body: | 734 bb.1: 735 liveins: $q0, $q1 736 737 ; CHECK-LABEL: name: test_v8i16_ult 738 ; CHECK: liveins: $q0, $q1 739 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 740 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 741 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(ult), [[COPY]](<8 x s16>), [[COPY1]] 742 ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 743 ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>) 744 ; CHECK: RET_ReallyLR implicit $d0 745 %0:_(<8 x s16>) = COPY $q0 746 %1:_(<8 x s16>) = COPY $q1 747 %2:_(<8 x s1>) = G_ICMP intpred(ult), %0(<8 x s16>), %1 748 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 749 $d0 = COPY %3(<8 x s8>) 750 RET_ReallyLR implicit $d0 751 752... 753--- 754name: test_v4i16_ult 755alignment: 4 756tracksRegLiveness: true 757registers: 758 - { id: 0, class: _ } 759 - { id: 1, class: _ } 760 - { id: 2, class: _ } 761 - { id: 3, class: _ } 762machineFunctionInfo: {} 763body: | 764 bb.1: 765 liveins: $d0, $d1 766 767 ; CHECK-LABEL: name: test_v4i16_ult 768 ; CHECK: liveins: $d0, $d1 769 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 770 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 771 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ult), [[COPY]](<4 x s16>), [[COPY1]] 772 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>) 773 ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>) 774 ; CHECK: RET_ReallyLR implicit $d0 775 %0:_(<4 x s16>) = COPY $d0 776 %1:_(<4 x s16>) = COPY $d1 777 %2:_(<4 x s1>) = G_ICMP intpred(ult), %0(<4 x s16>), %1 778 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 779 $d0 = COPY %3(<4 x s16>) 780 RET_ReallyLR implicit $d0 781 782... 783--- 784name: test_v16i8_ult 785alignment: 4 786tracksRegLiveness: true 787registers: 788 - { id: 0, class: _ } 789 - { id: 1, class: _ } 790 - { id: 2, class: _ } 791 - { id: 3, class: _ } 792machineFunctionInfo: {} 793body: | 794 bb.1: 795 liveins: $q0, $q1 796 797 ; CHECK-LABEL: name: test_v16i8_ult 798 ; CHECK: liveins: $q0, $q1 799 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 800 ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 801 ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ult), [[COPY]](<16 x s8>), [[COPY1]] 802 ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>) 803 ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>) 804 ; CHECK: RET_ReallyLR implicit $q0 805 %0:_(<16 x s8>) = COPY $q0 806 %1:_(<16 x s8>) = COPY $q1 807 %2:_(<16 x s1>) = G_ICMP intpred(ult), %0(<16 x s8>), %1 808 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 809 $q0 = COPY %3(<16 x s8>) 810 RET_ReallyLR implicit $q0 811 812... 813--- 814name: test_v8i8_ult 815alignment: 4 816tracksRegLiveness: true 817registers: 818 - { id: 0, class: _ } 819 - { id: 1, class: _ } 820 - { id: 2, class: _ } 821 - { id: 3, class: _ } 822machineFunctionInfo: {} 823body: | 824 bb.1: 825 liveins: $d0, $d1 826 827 ; CHECK-LABEL: name: test_v8i8_ult 828 ; CHECK: liveins: $d0, $d1 829 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 830 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 831 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ult), [[COPY]](<8 x s8>), [[COPY1]] 832 ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>) 833 ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>) 834 ; CHECK: RET_ReallyLR implicit $d0 835 %0:_(<8 x s8>) = COPY $d0 836 %1:_(<8 x s8>) = COPY $d1 837 %2:_(<8 x s1>) = G_ICMP intpred(ult), %0(<8 x s8>), %1 838 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 839 $d0 = COPY %3(<8 x s8>) 840 RET_ReallyLR implicit $d0 841 842... 843--- 844name: test_v2i64_ule 845alignment: 4 846tracksRegLiveness: true 847registers: 848 - { id: 0, class: _ } 849 - { id: 1, class: _ } 850 - { id: 2, class: _ } 851 - { id: 3, class: _ } 852machineFunctionInfo: {} 853body: | 854 bb.1: 855 liveins: $q0, $q1 856 857 ; CHECK-LABEL: name: test_v2i64_ule 858 ; CHECK: liveins: $q0, $q1 859 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 860 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 861 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ule), [[COPY]](<2 x s64>), [[COPY1]] 862 ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 863 ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>) 864 ; CHECK: RET_ReallyLR implicit $d0 865 %0:_(<2 x s64>) = COPY $q0 866 %1:_(<2 x s64>) = COPY $q1 867 %2:_(<2 x s1>) = G_ICMP intpred(ule), %0(<2 x s64>), %1 868 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 869 $d0 = COPY %3(<2 x s32>) 870 RET_ReallyLR implicit $d0 871 872... 873--- 874name: test_v4i32_ule 875alignment: 4 876tracksRegLiveness: true 877registers: 878 - { id: 0, class: _ } 879 - { id: 1, class: _ } 880 - { id: 2, class: _ } 881 - { id: 3, class: _ } 882machineFunctionInfo: {} 883body: | 884 bb.1: 885 liveins: $q0, $q1 886 887 ; CHECK-LABEL: name: test_v4i32_ule 888 ; CHECK: liveins: $q0, $q1 889 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 890 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 891 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ule), [[COPY]](<4 x s32>), [[COPY1]] 892 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 893 ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>) 894 ; CHECK: RET_ReallyLR implicit $d0 895 %0:_(<4 x s32>) = COPY $q0 896 %1:_(<4 x s32>) = COPY $q1 897 %2:_(<4 x s1>) = G_ICMP intpred(ule), %0(<4 x s32>), %1 898 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 899 $d0 = COPY %3(<4 x s16>) 900 RET_ReallyLR implicit $d0 901 902... 903--- 904name: test_v2i32_ule 905alignment: 4 906tracksRegLiveness: true 907registers: 908 - { id: 0, class: _ } 909 - { id: 1, class: _ } 910 - { id: 2, class: _ } 911 - { id: 3, class: _ } 912machineFunctionInfo: {} 913body: | 914 bb.1: 915 liveins: $d0, $d1 916 917 ; CHECK-LABEL: name: test_v2i32_ule 918 ; CHECK: liveins: $d0, $d1 919 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 920 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 921 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ule), [[COPY]](<2 x s32>), [[COPY1]] 922 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>) 923 ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>) 924 ; CHECK: RET_ReallyLR implicit $d0 925 %0:_(<2 x s32>) = COPY $d0 926 %1:_(<2 x s32>) = COPY $d1 927 %2:_(<2 x s1>) = G_ICMP intpred(ule), %0(<2 x s32>), %1 928 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 929 $d0 = COPY %3(<2 x s32>) 930 RET_ReallyLR implicit $d0 931 932... 933--- 934name: test_v8i16_ule 935alignment: 4 936tracksRegLiveness: true 937registers: 938 - { id: 0, class: _ } 939 - { id: 1, class: _ } 940 - { id: 2, class: _ } 941 - { id: 3, class: _ } 942machineFunctionInfo: {} 943body: | 944 bb.1: 945 liveins: $q0, $q1 946 947 ; CHECK-LABEL: name: test_v8i16_ule 948 ; CHECK: liveins: $q0, $q1 949 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 950 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 951 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(ule), [[COPY]](<8 x s16>), [[COPY1]] 952 ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 953 ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>) 954 ; CHECK: RET_ReallyLR implicit $d0 955 %0:_(<8 x s16>) = COPY $q0 956 %1:_(<8 x s16>) = COPY $q1 957 %2:_(<8 x s1>) = G_ICMP intpred(ule), %0(<8 x s16>), %1 958 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 959 $d0 = COPY %3(<8 x s8>) 960 RET_ReallyLR implicit $d0 961 962... 963--- 964name: test_v4i16_ule 965alignment: 4 966tracksRegLiveness: true 967registers: 968 - { id: 0, class: _ } 969 - { id: 1, class: _ } 970 - { id: 2, class: _ } 971 - { id: 3, class: _ } 972machineFunctionInfo: {} 973body: | 974 bb.1: 975 liveins: $d0, $d1 976 977 ; CHECK-LABEL: name: test_v4i16_ule 978 ; CHECK: liveins: $d0, $d1 979 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 980 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 981 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ule), [[COPY]](<4 x s16>), [[COPY1]] 982 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>) 983 ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>) 984 ; CHECK: RET_ReallyLR implicit $d0 985 %0:_(<4 x s16>) = COPY $d0 986 %1:_(<4 x s16>) = COPY $d1 987 %2:_(<4 x s1>) = G_ICMP intpred(ule), %0(<4 x s16>), %1 988 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 989 $d0 = COPY %3(<4 x s16>) 990 RET_ReallyLR implicit $d0 991 992... 993--- 994name: test_v16i8_ule 995alignment: 4 996tracksRegLiveness: true 997registers: 998 - { id: 0, class: _ } 999 - { id: 1, class: _ } 1000 - { id: 2, class: _ } 1001 - { id: 3, class: _ } 1002machineFunctionInfo: {} 1003body: | 1004 bb.1: 1005 liveins: $q0, $q1 1006 1007 ; CHECK-LABEL: name: test_v16i8_ule 1008 ; CHECK: liveins: $q0, $q1 1009 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 1010 ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 1011 ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ule), [[COPY]](<16 x s8>), [[COPY1]] 1012 ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>) 1013 ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>) 1014 ; CHECK: RET_ReallyLR implicit $q0 1015 %0:_(<16 x s8>) = COPY $q0 1016 %1:_(<16 x s8>) = COPY $q1 1017 %2:_(<16 x s1>) = G_ICMP intpred(ule), %0(<16 x s8>), %1 1018 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 1019 $q0 = COPY %3(<16 x s8>) 1020 RET_ReallyLR implicit $q0 1021 1022... 1023--- 1024name: test_v8i8_ule 1025alignment: 4 1026tracksRegLiveness: true 1027registers: 1028 - { id: 0, class: _ } 1029 - { id: 1, class: _ } 1030 - { id: 2, class: _ } 1031 - { id: 3, class: _ } 1032machineFunctionInfo: {} 1033body: | 1034 bb.1: 1035 liveins: $d0, $d1 1036 1037 ; CHECK-LABEL: name: test_v8i8_ule 1038 ; CHECK: liveins: $d0, $d1 1039 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 1040 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 1041 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ule), [[COPY]](<8 x s8>), [[COPY1]] 1042 ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>) 1043 ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>) 1044 ; CHECK: RET_ReallyLR implicit $d0 1045 %0:_(<8 x s8>) = COPY $d0 1046 %1:_(<8 x s8>) = COPY $d1 1047 %2:_(<8 x s1>) = G_ICMP intpred(ule), %0(<8 x s8>), %1 1048 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1049 $d0 = COPY %3(<8 x s8>) 1050 RET_ReallyLR implicit $d0 1051 1052... 1053--- 1054name: test_v2i64_sgt 1055alignment: 4 1056tracksRegLiveness: true 1057registers: 1058 - { id: 0, class: _ } 1059 - { id: 1, class: _ } 1060 - { id: 2, class: _ } 1061 - { id: 3, class: _ } 1062machineFunctionInfo: {} 1063body: | 1064 bb.1: 1065 liveins: $q0, $q1 1066 1067 ; CHECK-LABEL: name: test_v2i64_sgt 1068 ; CHECK: liveins: $q0, $q1 1069 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 1070 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 1071 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[COPY]](<2 x s64>), [[COPY1]] 1072 ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 1073 ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>) 1074 ; CHECK: RET_ReallyLR implicit $d0 1075 %0:_(<2 x s64>) = COPY $q0 1076 %1:_(<2 x s64>) = COPY $q1 1077 %2:_(<2 x s1>) = G_ICMP intpred(sgt), %0(<2 x s64>), %1 1078 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1079 $d0 = COPY %3(<2 x s32>) 1080 RET_ReallyLR implicit $d0 1081 1082... 1083--- 1084name: test_v4i32_sgt 1085alignment: 4 1086tracksRegLiveness: true 1087registers: 1088 - { id: 0, class: _ } 1089 - { id: 1, class: _ } 1090 - { id: 2, class: _ } 1091 - { id: 3, class: _ } 1092machineFunctionInfo: {} 1093body: | 1094 bb.1: 1095 liveins: $q0, $q1 1096 1097 ; CHECK-LABEL: name: test_v4i32_sgt 1098 ; CHECK: liveins: $q0, $q1 1099 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 1100 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 1101 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(sgt), [[COPY]](<4 x s32>), [[COPY1]] 1102 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 1103 ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>) 1104 ; CHECK: RET_ReallyLR implicit $d0 1105 %0:_(<4 x s32>) = COPY $q0 1106 %1:_(<4 x s32>) = COPY $q1 1107 %2:_(<4 x s1>) = G_ICMP intpred(sgt), %0(<4 x s32>), %1 1108 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1109 $d0 = COPY %3(<4 x s16>) 1110 RET_ReallyLR implicit $d0 1111 1112... 1113--- 1114name: test_v2i32_sgt 1115alignment: 4 1116tracksRegLiveness: true 1117registers: 1118 - { id: 0, class: _ } 1119 - { id: 1, class: _ } 1120 - { id: 2, class: _ } 1121 - { id: 3, class: _ } 1122machineFunctionInfo: {} 1123body: | 1124 bb.1: 1125 liveins: $d0, $d1 1126 1127 ; CHECK-LABEL: name: test_v2i32_sgt 1128 ; CHECK: liveins: $d0, $d1 1129 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 1130 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 1131 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sgt), [[COPY]](<2 x s32>), [[COPY1]] 1132 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>) 1133 ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>) 1134 ; CHECK: RET_ReallyLR implicit $d0 1135 %0:_(<2 x s32>) = COPY $d0 1136 %1:_(<2 x s32>) = COPY $d1 1137 %2:_(<2 x s1>) = G_ICMP intpred(sgt), %0(<2 x s32>), %1 1138 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1139 $d0 = COPY %3(<2 x s32>) 1140 RET_ReallyLR implicit $d0 1141 1142... 1143--- 1144name: test_v8i16_sgt 1145alignment: 4 1146tracksRegLiveness: true 1147registers: 1148 - { id: 0, class: _ } 1149 - { id: 1, class: _ } 1150 - { id: 2, class: _ } 1151 - { id: 3, class: _ } 1152machineFunctionInfo: {} 1153body: | 1154 bb.1: 1155 liveins: $q0, $q1 1156 1157 ; CHECK-LABEL: name: test_v8i16_sgt 1158 ; CHECK: liveins: $q0, $q1 1159 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 1160 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 1161 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(sgt), [[COPY]](<8 x s16>), [[COPY1]] 1162 ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 1163 ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>) 1164 ; CHECK: RET_ReallyLR implicit $d0 1165 %0:_(<8 x s16>) = COPY $q0 1166 %1:_(<8 x s16>) = COPY $q1 1167 %2:_(<8 x s1>) = G_ICMP intpred(sgt), %0(<8 x s16>), %1 1168 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1169 $d0 = COPY %3(<8 x s8>) 1170 RET_ReallyLR implicit $d0 1171 1172... 1173--- 1174name: test_v4i16_sgt 1175alignment: 4 1176tracksRegLiveness: true 1177registers: 1178 - { id: 0, class: _ } 1179 - { id: 1, class: _ } 1180 - { id: 2, class: _ } 1181 - { id: 3, class: _ } 1182machineFunctionInfo: {} 1183body: | 1184 bb.1: 1185 liveins: $d0, $d1 1186 1187 ; CHECK-LABEL: name: test_v4i16_sgt 1188 ; CHECK: liveins: $d0, $d1 1189 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 1190 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 1191 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sgt), [[COPY]](<4 x s16>), [[COPY1]] 1192 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>) 1193 ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>) 1194 ; CHECK: RET_ReallyLR implicit $d0 1195 %0:_(<4 x s16>) = COPY $d0 1196 %1:_(<4 x s16>) = COPY $d1 1197 %2:_(<4 x s1>) = G_ICMP intpred(sgt), %0(<4 x s16>), %1 1198 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1199 $d0 = COPY %3(<4 x s16>) 1200 RET_ReallyLR implicit $d0 1201 1202... 1203--- 1204name: test_v16i8_sgt 1205alignment: 4 1206tracksRegLiveness: true 1207registers: 1208 - { id: 0, class: _ } 1209 - { id: 1, class: _ } 1210 - { id: 2, class: _ } 1211 - { id: 3, class: _ } 1212machineFunctionInfo: {} 1213body: | 1214 bb.1: 1215 liveins: $q0, $q1 1216 1217 ; CHECK-LABEL: name: test_v16i8_sgt 1218 ; CHECK: liveins: $q0, $q1 1219 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 1220 ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 1221 ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sgt), [[COPY]](<16 x s8>), [[COPY1]] 1222 ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>) 1223 ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>) 1224 ; CHECK: RET_ReallyLR implicit $q0 1225 %0:_(<16 x s8>) = COPY $q0 1226 %1:_(<16 x s8>) = COPY $q1 1227 %2:_(<16 x s1>) = G_ICMP intpred(sgt), %0(<16 x s8>), %1 1228 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 1229 $q0 = COPY %3(<16 x s8>) 1230 RET_ReallyLR implicit $q0 1231 1232... 1233--- 1234name: test_v8i8_sgt 1235alignment: 4 1236tracksRegLiveness: true 1237registers: 1238 - { id: 0, class: _ } 1239 - { id: 1, class: _ } 1240 - { id: 2, class: _ } 1241 - { id: 3, class: _ } 1242machineFunctionInfo: {} 1243body: | 1244 bb.1: 1245 liveins: $d0, $d1 1246 1247 ; CHECK-LABEL: name: test_v8i8_sgt 1248 ; CHECK: liveins: $d0, $d1 1249 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 1250 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 1251 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sgt), [[COPY]](<8 x s8>), [[COPY1]] 1252 ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>) 1253 ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>) 1254 ; CHECK: RET_ReallyLR implicit $d0 1255 %0:_(<8 x s8>) = COPY $d0 1256 %1:_(<8 x s8>) = COPY $d1 1257 %2:_(<8 x s1>) = G_ICMP intpred(sgt), %0(<8 x s8>), %1 1258 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1259 $d0 = COPY %3(<8 x s8>) 1260 RET_ReallyLR implicit $d0 1261 1262... 1263--- 1264name: test_v2i64_sge 1265alignment: 4 1266tracksRegLiveness: true 1267registers: 1268 - { id: 0, class: _ } 1269 - { id: 1, class: _ } 1270 - { id: 2, class: _ } 1271 - { id: 3, class: _ } 1272machineFunctionInfo: {} 1273body: | 1274 bb.1: 1275 liveins: $q0, $q1 1276 1277 ; CHECK-LABEL: name: test_v2i64_sge 1278 ; CHECK: liveins: $q0, $q1 1279 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 1280 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 1281 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sge), [[COPY]](<2 x s64>), [[COPY1]] 1282 ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 1283 ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>) 1284 ; CHECK: RET_ReallyLR implicit $d0 1285 %0:_(<2 x s64>) = COPY $q0 1286 %1:_(<2 x s64>) = COPY $q1 1287 %2:_(<2 x s1>) = G_ICMP intpred(sge), %0(<2 x s64>), %1 1288 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1289 $d0 = COPY %3(<2 x s32>) 1290 RET_ReallyLR implicit $d0 1291 1292... 1293--- 1294name: test_v4i32_sge 1295alignment: 4 1296tracksRegLiveness: true 1297registers: 1298 - { id: 0, class: _ } 1299 - { id: 1, class: _ } 1300 - { id: 2, class: _ } 1301 - { id: 3, class: _ } 1302machineFunctionInfo: {} 1303body: | 1304 bb.1: 1305 liveins: $q0, $q1 1306 1307 ; CHECK-LABEL: name: test_v4i32_sge 1308 ; CHECK: liveins: $q0, $q1 1309 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 1310 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 1311 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(sge), [[COPY]](<4 x s32>), [[COPY1]] 1312 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 1313 ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>) 1314 ; CHECK: RET_ReallyLR implicit $d0 1315 %0:_(<4 x s32>) = COPY $q0 1316 %1:_(<4 x s32>) = COPY $q1 1317 %2:_(<4 x s1>) = G_ICMP intpred(sge), %0(<4 x s32>), %1 1318 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1319 $d0 = COPY %3(<4 x s16>) 1320 RET_ReallyLR implicit $d0 1321 1322... 1323--- 1324name: test_v2i32_sge 1325alignment: 4 1326tracksRegLiveness: true 1327registers: 1328 - { id: 0, class: _ } 1329 - { id: 1, class: _ } 1330 - { id: 2, class: _ } 1331 - { id: 3, class: _ } 1332machineFunctionInfo: {} 1333body: | 1334 bb.1: 1335 liveins: $d0, $d1 1336 1337 ; CHECK-LABEL: name: test_v2i32_sge 1338 ; CHECK: liveins: $d0, $d1 1339 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 1340 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 1341 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sge), [[COPY]](<2 x s32>), [[COPY1]] 1342 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>) 1343 ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>) 1344 ; CHECK: RET_ReallyLR implicit $d0 1345 %0:_(<2 x s32>) = COPY $d0 1346 %1:_(<2 x s32>) = COPY $d1 1347 %2:_(<2 x s1>) = G_ICMP intpred(sge), %0(<2 x s32>), %1 1348 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1349 $d0 = COPY %3(<2 x s32>) 1350 RET_ReallyLR implicit $d0 1351 1352... 1353--- 1354name: test_v8i16_sge 1355alignment: 4 1356tracksRegLiveness: true 1357registers: 1358 - { id: 0, class: _ } 1359 - { id: 1, class: _ } 1360 - { id: 2, class: _ } 1361 - { id: 3, class: _ } 1362machineFunctionInfo: {} 1363body: | 1364 bb.1: 1365 liveins: $q0, $q1 1366 1367 ; CHECK-LABEL: name: test_v8i16_sge 1368 ; CHECK: liveins: $q0, $q1 1369 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 1370 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 1371 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(sge), [[COPY]](<8 x s16>), [[COPY1]] 1372 ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 1373 ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>) 1374 ; CHECK: RET_ReallyLR implicit $d0 1375 %0:_(<8 x s16>) = COPY $q0 1376 %1:_(<8 x s16>) = COPY $q1 1377 %2:_(<8 x s1>) = G_ICMP intpred(sge), %0(<8 x s16>), %1 1378 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1379 $d0 = COPY %3(<8 x s8>) 1380 RET_ReallyLR implicit $d0 1381 1382... 1383--- 1384name: test_v4i16_sge 1385alignment: 4 1386tracksRegLiveness: true 1387registers: 1388 - { id: 0, class: _ } 1389 - { id: 1, class: _ } 1390 - { id: 2, class: _ } 1391 - { id: 3, class: _ } 1392machineFunctionInfo: {} 1393body: | 1394 bb.1: 1395 liveins: $d0, $d1 1396 1397 ; CHECK-LABEL: name: test_v4i16_sge 1398 ; CHECK: liveins: $d0, $d1 1399 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 1400 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 1401 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sge), [[COPY]](<4 x s16>), [[COPY1]] 1402 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>) 1403 ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>) 1404 ; CHECK: RET_ReallyLR implicit $d0 1405 %0:_(<4 x s16>) = COPY $d0 1406 %1:_(<4 x s16>) = COPY $d1 1407 %2:_(<4 x s1>) = G_ICMP intpred(sge), %0(<4 x s16>), %1 1408 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1409 $d0 = COPY %3(<4 x s16>) 1410 RET_ReallyLR implicit $d0 1411 1412... 1413--- 1414name: test_v16i8_sge 1415alignment: 4 1416tracksRegLiveness: true 1417registers: 1418 - { id: 0, class: _ } 1419 - { id: 1, class: _ } 1420 - { id: 2, class: _ } 1421 - { id: 3, class: _ } 1422machineFunctionInfo: {} 1423body: | 1424 bb.1: 1425 liveins: $q0, $q1 1426 1427 ; CHECK-LABEL: name: test_v16i8_sge 1428 ; CHECK: liveins: $q0, $q1 1429 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 1430 ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 1431 ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sge), [[COPY]](<16 x s8>), [[COPY1]] 1432 ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>) 1433 ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>) 1434 ; CHECK: RET_ReallyLR implicit $q0 1435 %0:_(<16 x s8>) = COPY $q0 1436 %1:_(<16 x s8>) = COPY $q1 1437 %2:_(<16 x s1>) = G_ICMP intpred(sge), %0(<16 x s8>), %1 1438 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 1439 $q0 = COPY %3(<16 x s8>) 1440 RET_ReallyLR implicit $q0 1441 1442... 1443--- 1444name: test_v8i8_sge 1445alignment: 4 1446tracksRegLiveness: true 1447registers: 1448 - { id: 0, class: _ } 1449 - { id: 1, class: _ } 1450 - { id: 2, class: _ } 1451 - { id: 3, class: _ } 1452machineFunctionInfo: {} 1453body: | 1454 bb.1: 1455 liveins: $d0, $d1 1456 1457 ; CHECK-LABEL: name: test_v8i8_sge 1458 ; CHECK: liveins: $d0, $d1 1459 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 1460 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 1461 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sge), [[COPY]](<8 x s8>), [[COPY1]] 1462 ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>) 1463 ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>) 1464 ; CHECK: RET_ReallyLR implicit $d0 1465 %0:_(<8 x s8>) = COPY $d0 1466 %1:_(<8 x s8>) = COPY $d1 1467 %2:_(<8 x s1>) = G_ICMP intpred(sge), %0(<8 x s8>), %1 1468 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1469 $d0 = COPY %3(<8 x s8>) 1470 RET_ReallyLR implicit $d0 1471 1472... 1473--- 1474name: test_v2i64_slt 1475alignment: 4 1476tracksRegLiveness: true 1477registers: 1478 - { id: 0, class: _ } 1479 - { id: 1, class: _ } 1480 - { id: 2, class: _ } 1481 - { id: 3, class: _ } 1482machineFunctionInfo: {} 1483body: | 1484 bb.1: 1485 liveins: $q0, $q1 1486 1487 ; CHECK-LABEL: name: test_v2i64_slt 1488 ; CHECK: liveins: $q0, $q1 1489 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 1490 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 1491 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[COPY]](<2 x s64>), [[COPY1]] 1492 ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 1493 ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>) 1494 ; CHECK: RET_ReallyLR implicit $d0 1495 %0:_(<2 x s64>) = COPY $q0 1496 %1:_(<2 x s64>) = COPY $q1 1497 %2:_(<2 x s1>) = G_ICMP intpred(slt), %0(<2 x s64>), %1 1498 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1499 $d0 = COPY %3(<2 x s32>) 1500 RET_ReallyLR implicit $d0 1501 1502... 1503--- 1504name: test_v4i32_slt 1505alignment: 4 1506tracksRegLiveness: true 1507registers: 1508 - { id: 0, class: _ } 1509 - { id: 1, class: _ } 1510 - { id: 2, class: _ } 1511 - { id: 3, class: _ } 1512machineFunctionInfo: {} 1513body: | 1514 bb.1: 1515 liveins: $q0, $q1 1516 1517 ; CHECK-LABEL: name: test_v4i32_slt 1518 ; CHECK: liveins: $q0, $q1 1519 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 1520 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 1521 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(slt), [[COPY]](<4 x s32>), [[COPY1]] 1522 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 1523 ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>) 1524 ; CHECK: RET_ReallyLR implicit $d0 1525 %0:_(<4 x s32>) = COPY $q0 1526 %1:_(<4 x s32>) = COPY $q1 1527 %2:_(<4 x s1>) = G_ICMP intpred(slt), %0(<4 x s32>), %1 1528 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1529 $d0 = COPY %3(<4 x s16>) 1530 RET_ReallyLR implicit $d0 1531 1532... 1533--- 1534name: test_v2i32_slt 1535alignment: 4 1536tracksRegLiveness: true 1537registers: 1538 - { id: 0, class: _ } 1539 - { id: 1, class: _ } 1540 - { id: 2, class: _ } 1541 - { id: 3, class: _ } 1542machineFunctionInfo: {} 1543body: | 1544 bb.1: 1545 liveins: $d0, $d1 1546 1547 ; CHECK-LABEL: name: test_v2i32_slt 1548 ; CHECK: liveins: $d0, $d1 1549 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 1550 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 1551 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(slt), [[COPY]](<2 x s32>), [[COPY1]] 1552 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>) 1553 ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>) 1554 ; CHECK: RET_ReallyLR implicit $d0 1555 %0:_(<2 x s32>) = COPY $d0 1556 %1:_(<2 x s32>) = COPY $d1 1557 %2:_(<2 x s1>) = G_ICMP intpred(slt), %0(<2 x s32>), %1 1558 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1559 $d0 = COPY %3(<2 x s32>) 1560 RET_ReallyLR implicit $d0 1561 1562... 1563--- 1564name: test_v8i16_slt 1565alignment: 4 1566tracksRegLiveness: true 1567registers: 1568 - { id: 0, class: _ } 1569 - { id: 1, class: _ } 1570 - { id: 2, class: _ } 1571 - { id: 3, class: _ } 1572machineFunctionInfo: {} 1573body: | 1574 bb.1: 1575 liveins: $q0, $q1 1576 1577 ; CHECK-LABEL: name: test_v8i16_slt 1578 ; CHECK: liveins: $q0, $q1 1579 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 1580 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 1581 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(slt), [[COPY]](<8 x s16>), [[COPY1]] 1582 ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 1583 ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>) 1584 ; CHECK: RET_ReallyLR implicit $d0 1585 %0:_(<8 x s16>) = COPY $q0 1586 %1:_(<8 x s16>) = COPY $q1 1587 %2:_(<8 x s1>) = G_ICMP intpred(slt), %0(<8 x s16>), %1 1588 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1589 $d0 = COPY %3(<8 x s8>) 1590 RET_ReallyLR implicit $d0 1591 1592... 1593--- 1594name: test_v4i16_slt 1595alignment: 4 1596tracksRegLiveness: true 1597registers: 1598 - { id: 0, class: _ } 1599 - { id: 1, class: _ } 1600 - { id: 2, class: _ } 1601 - { id: 3, class: _ } 1602machineFunctionInfo: {} 1603body: | 1604 bb.1: 1605 liveins: $d0, $d1 1606 1607 ; CHECK-LABEL: name: test_v4i16_slt 1608 ; CHECK: liveins: $d0, $d1 1609 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 1610 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 1611 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(slt), [[COPY]](<4 x s16>), [[COPY1]] 1612 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>) 1613 ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>) 1614 ; CHECK: RET_ReallyLR implicit $d0 1615 %0:_(<4 x s16>) = COPY $d0 1616 %1:_(<4 x s16>) = COPY $d1 1617 %2:_(<4 x s1>) = G_ICMP intpred(slt), %0(<4 x s16>), %1 1618 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1619 $d0 = COPY %3(<4 x s16>) 1620 RET_ReallyLR implicit $d0 1621 1622... 1623--- 1624name: test_v16i8_slt 1625alignment: 4 1626tracksRegLiveness: true 1627registers: 1628 - { id: 0, class: _ } 1629 - { id: 1, class: _ } 1630 - { id: 2, class: _ } 1631 - { id: 3, class: _ } 1632machineFunctionInfo: {} 1633body: | 1634 bb.1: 1635 liveins: $q0, $q1 1636 1637 ; CHECK-LABEL: name: test_v16i8_slt 1638 ; CHECK: liveins: $q0, $q1 1639 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 1640 ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 1641 ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(slt), [[COPY]](<16 x s8>), [[COPY1]] 1642 ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>) 1643 ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>) 1644 ; CHECK: RET_ReallyLR implicit $q0 1645 %0:_(<16 x s8>) = COPY $q0 1646 %1:_(<16 x s8>) = COPY $q1 1647 %2:_(<16 x s1>) = G_ICMP intpred(slt), %0(<16 x s8>), %1 1648 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 1649 $q0 = COPY %3(<16 x s8>) 1650 RET_ReallyLR implicit $q0 1651 1652... 1653--- 1654name: test_v8i8_slt 1655alignment: 4 1656tracksRegLiveness: true 1657registers: 1658 - { id: 0, class: _ } 1659 - { id: 1, class: _ } 1660 - { id: 2, class: _ } 1661 - { id: 3, class: _ } 1662machineFunctionInfo: {} 1663body: | 1664 bb.1: 1665 liveins: $d0, $d1 1666 1667 ; CHECK-LABEL: name: test_v8i8_slt 1668 ; CHECK: liveins: $d0, $d1 1669 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 1670 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 1671 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(slt), [[COPY]](<8 x s8>), [[COPY1]] 1672 ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>) 1673 ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>) 1674 ; CHECK: RET_ReallyLR implicit $d0 1675 %0:_(<8 x s8>) = COPY $d0 1676 %1:_(<8 x s8>) = COPY $d1 1677 %2:_(<8 x s1>) = G_ICMP intpred(slt), %0(<8 x s8>), %1 1678 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1679 $d0 = COPY %3(<8 x s8>) 1680 RET_ReallyLR implicit $d0 1681 1682... 1683--- 1684name: test_v2i64_sle 1685alignment: 4 1686tracksRegLiveness: true 1687registers: 1688 - { id: 0, class: _ } 1689 - { id: 1, class: _ } 1690 - { id: 2, class: _ } 1691 - { id: 3, class: _ } 1692machineFunctionInfo: {} 1693body: | 1694 bb.1: 1695 liveins: $q0, $q1 1696 1697 ; CHECK-LABEL: name: test_v2i64_sle 1698 ; CHECK: liveins: $q0, $q1 1699 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 1700 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 1701 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sle), [[COPY]](<2 x s64>), [[COPY1]] 1702 ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 1703 ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>) 1704 ; CHECK: RET_ReallyLR implicit $d0 1705 %0:_(<2 x s64>) = COPY $q0 1706 %1:_(<2 x s64>) = COPY $q1 1707 %2:_(<2 x s1>) = G_ICMP intpred(sle), %0(<2 x s64>), %1 1708 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1709 $d0 = COPY %3(<2 x s32>) 1710 RET_ReallyLR implicit $d0 1711 1712... 1713--- 1714name: test_v4i32_sle 1715alignment: 4 1716tracksRegLiveness: true 1717registers: 1718 - { id: 0, class: _ } 1719 - { id: 1, class: _ } 1720 - { id: 2, class: _ } 1721 - { id: 3, class: _ } 1722machineFunctionInfo: {} 1723body: | 1724 bb.1: 1725 liveins: $q0, $q1 1726 1727 ; CHECK-LABEL: name: test_v4i32_sle 1728 ; CHECK: liveins: $q0, $q1 1729 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 1730 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 1731 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(sle), [[COPY]](<4 x s32>), [[COPY1]] 1732 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 1733 ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>) 1734 ; CHECK: RET_ReallyLR implicit $d0 1735 %0:_(<4 x s32>) = COPY $q0 1736 %1:_(<4 x s32>) = COPY $q1 1737 %2:_(<4 x s1>) = G_ICMP intpred(sle), %0(<4 x s32>), %1 1738 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1739 $d0 = COPY %3(<4 x s16>) 1740 RET_ReallyLR implicit $d0 1741 1742... 1743--- 1744name: test_v2i32_sle 1745alignment: 4 1746tracksRegLiveness: true 1747registers: 1748 - { id: 0, class: _ } 1749 - { id: 1, class: _ } 1750 - { id: 2, class: _ } 1751 - { id: 3, class: _ } 1752machineFunctionInfo: {} 1753body: | 1754 bb.1: 1755 liveins: $d0, $d1 1756 1757 ; CHECK-LABEL: name: test_v2i32_sle 1758 ; CHECK: liveins: $d0, $d1 1759 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 1760 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 1761 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sle), [[COPY]](<2 x s32>), [[COPY1]] 1762 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>) 1763 ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>) 1764 ; CHECK: RET_ReallyLR implicit $d0 1765 %0:_(<2 x s32>) = COPY $d0 1766 %1:_(<2 x s32>) = COPY $d1 1767 %2:_(<2 x s1>) = G_ICMP intpred(sle), %0(<2 x s32>), %1 1768 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1769 $d0 = COPY %3(<2 x s32>) 1770 RET_ReallyLR implicit $d0 1771 1772... 1773--- 1774name: test_v8i16_sle 1775alignment: 4 1776tracksRegLiveness: true 1777registers: 1778 - { id: 0, class: _ } 1779 - { id: 1, class: _ } 1780 - { id: 2, class: _ } 1781 - { id: 3, class: _ } 1782machineFunctionInfo: {} 1783body: | 1784 bb.1: 1785 liveins: $q0, $q1 1786 1787 ; CHECK-LABEL: name: test_v8i16_sle 1788 ; CHECK: liveins: $q0, $q1 1789 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 1790 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 1791 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(sle), [[COPY]](<8 x s16>), [[COPY1]] 1792 ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 1793 ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>) 1794 ; CHECK: RET_ReallyLR implicit $d0 1795 %0:_(<8 x s16>) = COPY $q0 1796 %1:_(<8 x s16>) = COPY $q1 1797 %2:_(<8 x s1>) = G_ICMP intpred(sle), %0(<8 x s16>), %1 1798 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1799 $d0 = COPY %3(<8 x s8>) 1800 RET_ReallyLR implicit $d0 1801 1802... 1803--- 1804name: test_v4i16_sle 1805alignment: 4 1806tracksRegLiveness: true 1807registers: 1808 - { id: 0, class: _ } 1809 - { id: 1, class: _ } 1810 - { id: 2, class: _ } 1811 - { id: 3, class: _ } 1812machineFunctionInfo: {} 1813body: | 1814 bb.1: 1815 liveins: $d0, $d1 1816 1817 ; CHECK-LABEL: name: test_v4i16_sle 1818 ; CHECK: liveins: $d0, $d1 1819 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 1820 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 1821 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sle), [[COPY]](<4 x s16>), [[COPY1]] 1822 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>) 1823 ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>) 1824 ; CHECK: RET_ReallyLR implicit $d0 1825 %0:_(<4 x s16>) = COPY $d0 1826 %1:_(<4 x s16>) = COPY $d1 1827 %2:_(<4 x s1>) = G_ICMP intpred(sle), %0(<4 x s16>), %1 1828 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1829 $d0 = COPY %3(<4 x s16>) 1830 RET_ReallyLR implicit $d0 1831 1832... 1833--- 1834name: test_v16i8_sle 1835alignment: 4 1836tracksRegLiveness: true 1837registers: 1838 - { id: 0, class: _ } 1839 - { id: 1, class: _ } 1840 - { id: 2, class: _ } 1841 - { id: 3, class: _ } 1842machineFunctionInfo: {} 1843body: | 1844 bb.1: 1845 liveins: $q0, $q1 1846 1847 ; CHECK-LABEL: name: test_v16i8_sle 1848 ; CHECK: liveins: $q0, $q1 1849 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 1850 ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 1851 ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sle), [[COPY]](<16 x s8>), [[COPY1]] 1852 ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>) 1853 ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>) 1854 ; CHECK: RET_ReallyLR implicit $q0 1855 %0:_(<16 x s8>) = COPY $q0 1856 %1:_(<16 x s8>) = COPY $q1 1857 %2:_(<16 x s1>) = G_ICMP intpred(sle), %0(<16 x s8>), %1 1858 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 1859 $q0 = COPY %3(<16 x s8>) 1860 RET_ReallyLR implicit $q0 1861 1862... 1863--- 1864name: test_v8i8_sle 1865alignment: 4 1866tracksRegLiveness: true 1867registers: 1868 - { id: 0, class: _ } 1869 - { id: 1, class: _ } 1870 - { id: 2, class: _ } 1871 - { id: 3, class: _ } 1872machineFunctionInfo: {} 1873body: | 1874 bb.1: 1875 liveins: $d0, $d1 1876 1877 ; CHECK-LABEL: name: test_v8i8_sle 1878 ; CHECK: liveins: $d0, $d1 1879 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 1880 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 1881 ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sle), [[COPY]](<8 x s8>), [[COPY1]] 1882 ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>) 1883 ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>) 1884 ; CHECK: RET_ReallyLR implicit $d0 1885 %0:_(<8 x s8>) = COPY $d0 1886 %1:_(<8 x s8>) = COPY $d1 1887 %2:_(<8 x s1>) = G_ICMP intpred(sle), %0(<8 x s8>), %1 1888 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1889 $d0 = COPY %3(<8 x s8>) 1890 RET_ReallyLR implicit $d0 1891 1892... 1893--- 1894name: test_v2p0_eq 1895alignment: 4 1896tracksRegLiveness: true 1897registers: 1898 - { id: 0, class: _ } 1899 - { id: 1, class: _ } 1900 - { id: 2, class: _ } 1901 - { id: 3, class: _ } 1902machineFunctionInfo: {} 1903body: | 1904 bb.1: 1905 liveins: $q0, $q1 1906 1907 ; CHECK-LABEL: name: test_v2p0_eq 1908 ; CHECK: liveins: $q0, $q1 1909 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0 1910 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $q1 1911 ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[COPY]](<2 x p0>), [[COPY1]] 1912 ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 1913 ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>) 1914 ; CHECK: RET_ReallyLR implicit $d0 1915 %0:_(<2 x p0>) = COPY $q0 1916 %1:_(<2 x p0>) = COPY $q1 1917 %2:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x p0>), %1 1918 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1919 $d0 = COPY %3(<2 x s32>) 1920 RET_ReallyLR implicit $d0 1921 1922... 1923--- 1924name: icmp_8xs1 1925alignment: 4 1926tracksRegLiveness: true 1927liveins: 1928 - { reg: '$q0' } 1929 - { reg: '$q1' } 1930 - { reg: '$q2' } 1931 - { reg: '$q3' } 1932body: | 1933 bb.1: 1934 liveins: $q0, $q1, $q2, $q3 1935 1936 ; CHECK-LABEL: name: icmp_8xs1 1937 ; CHECK: liveins: $q0, $q1, $q2, $q3 1938 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 1939 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 1940 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2 1941 ; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3 1942 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY2]] 1943 ; CHECK: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY1]](<4 x s32>), [[COPY3]] 1944 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 1945 ; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>) 1946 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>) 1947 ; CHECK: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>) 1948 ; CHECK: $d0 = COPY [[TRUNC2]](<8 x s8>) 1949 ; CHECK: RET_ReallyLR implicit $d0 1950 %2:_(<4 x s32>) = COPY $q0 1951 %3:_(<4 x s32>) = COPY $q1 1952 %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>) 1953 %4:_(<4 x s32>) = COPY $q2 1954 %5:_(<4 x s32>) = COPY $q3 1955 %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>) 1956 %6:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s32>), %1 1957 %7:_(<8 x s8>) = G_ANYEXT %6(<8 x s1>) 1958 $d0 = COPY %7(<8 x s8>) 1959 RET_ReallyLR implicit $d0 1960... 1961--- 1962name: icmp_8xs32 1963alignment: 4 1964tracksRegLiveness: true 1965liveins: 1966 - { reg: '$q0' } 1967 - { reg: '$q1' } 1968 - { reg: '$q2' } 1969 - { reg: '$q3' } 1970body: | 1971 bb.1: 1972 liveins: $q0, $q1, $q2, $q3 1973 1974 ; CHECK-LABEL: name: icmp_8xs32 1975 ; CHECK: liveins: $q0, $q1, $q2, $q3 1976 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 1977 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 1978 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2 1979 ; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3 1980 ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY2]] 1981 ; CHECK: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY1]](<4 x s32>), [[COPY3]] 1982 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 1983 ; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>) 1984 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>) 1985 ; CHECK: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>) 1986 ; CHECK: $d0 = COPY [[TRUNC2]](<8 x s8>) 1987 ; CHECK: RET_ReallyLR implicit $d0 1988 %2:_(<4 x s32>) = COPY $q0 1989 %3:_(<4 x s32>) = COPY $q1 1990 %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>) 1991 %4:_(<4 x s32>) = COPY $q2 1992 %5:_(<4 x s32>) = COPY $q3 1993 %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>) 1994 %6:_(<8 x s32>) = G_ICMP intpred(eq), %0(<8 x s32>), %1 1995 %7:_(<8 x s8>) = G_TRUNC %6(<8 x s32>) 1996 $d0 = COPY %7(<8 x s8>) 1997 RET_ReallyLR implicit $d0 1998... 1999--- 2000name: fcmp_8xs1 2001alignment: 4 2002tracksRegLiveness: true 2003liveins: 2004 - { reg: '$q0' } 2005 - { reg: '$q1' } 2006 - { reg: '$q2' } 2007 - { reg: '$q3' } 2008body: | 2009 bb.1: 2010 liveins: $q0, $q1, $q2, $q3 2011 2012 ; CHECK-LABEL: name: fcmp_8xs1 2013 ; CHECK: liveins: $q0, $q1, $q2, $q3 2014 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 2015 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 2016 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2 2017 ; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3 2018 ; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(one), [[COPY]](<4 x s32>), [[COPY2]] 2019 ; CHECK: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(one), [[COPY1]](<4 x s32>), [[COPY3]] 2020 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>) 2021 ; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>) 2022 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>) 2023 ; CHECK: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>) 2024 ; CHECK: $d0 = COPY [[TRUNC2]](<8 x s8>) 2025 ; CHECK: RET_ReallyLR implicit $d0 2026 %2:_(<4 x s32>) = COPY $q0 2027 %3:_(<4 x s32>) = COPY $q1 2028 %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>) 2029 %4:_(<4 x s32>) = COPY $q2 2030 %5:_(<4 x s32>) = COPY $q3 2031 %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>) 2032 %6:_(<8 x s1>) = G_FCMP floatpred(one), %0(<8 x s32>), %1 2033 %7:_(<8 x s8>) = G_ANYEXT %6(<8 x s1>) 2034 $d0 = COPY %7(<8 x s8>) 2035 RET_ReallyLR implicit $d0 2036... 2037--- 2038name: fcmp_8xs32 2039alignment: 4 2040tracksRegLiveness: true 2041liveins: 2042 - { reg: '$q0' } 2043 - { reg: '$q1' } 2044 - { reg: '$q2' } 2045 - { reg: '$q3' } 2046body: | 2047 bb.1: 2048 liveins: $q0, $q1, $q2, $q3 2049 2050 ; CHECK-LABEL: name: fcmp_8xs32 2051 ; CHECK: liveins: $q0, $q1, $q2, $q3 2052 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 2053 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 2054 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2 2055 ; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3 2056 ; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(oeq), [[COPY]](<4 x s32>), [[COPY2]] 2057 ; CHECK: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(oeq), [[COPY1]](<4 x s32>), [[COPY3]] 2058 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>) 2059 ; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>) 2060 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>) 2061 ; CHECK: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>) 2062 ; CHECK: $d0 = COPY [[TRUNC2]](<8 x s8>) 2063 ; CHECK: RET_ReallyLR implicit $d0 2064 %2:_(<4 x s32>) = COPY $q0 2065 %3:_(<4 x s32>) = COPY $q1 2066 %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>) 2067 %4:_(<4 x s32>) = COPY $q2 2068 %5:_(<4 x s32>) = COPY $q3 2069 %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>) 2070 %6:_(<8 x s32>) = G_FCMP floatpred(oeq), %0(<8 x s32>), %1 2071 %7:_(<8 x s8>) = G_TRUNC %6(<8 x s32>) 2072 $d0 = COPY %7(<8 x s8>) 2073 RET_ReallyLR implicit $d0 2074... 2075--- 2076name: fcmp_v4s32 2077alignment: 4 2078tracksRegLiveness: true 2079registers: 2080 - { id: 0, class: _ } 2081 - { id: 1, class: _ } 2082 - { id: 2, class: _ } 2083 - { id: 3, class: _ } 2084machineFunctionInfo: {} 2085body: | 2086 bb.1: 2087 liveins: $q0, $q1 2088 2089 ; CHECK-LABEL: name: fcmp_v4s32 2090 ; CHECK: liveins: $q0, $q1 2091 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 2092 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 2093 ; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(olt), [[COPY]](<4 x s32>), [[COPY1]] 2094 ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>) 2095 ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>) 2096 ; CHECK: RET_ReallyLR implicit $d0 2097 %0:_(<4 x s32>) = COPY $q0 2098 %1:_(<4 x s32>) = COPY $q1 2099 %2:_(<4 x s1>) = G_FCMP floatpred(olt), %0(<4 x s32>), %1 2100 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 2101 $d0 = COPY %3(<4 x s16>) 2102 RET_ReallyLR implicit $d0 2103 2104... 2105