1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s 3--- | 4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 5 target triple = "aarch64" 6 7 define i32 @ld_zext_i24(i24* %ptr, i24* %ptr2) { 8 %load = load i24, i24* %ptr, align 1 9 %ext = zext i24 %load to i32 10 ret i32 %ext 11 } 12 13... 14--- 15name: ld_zext_i24 16alignment: 4 17tracksRegLiveness: true 18machineFunctionInfo: {} 19body: | 20 bb.1 (%ir-block.0): 21 liveins: $x0, $x1 22 23 ; CHECK-LABEL: name: ld_zext_i24 24 ; CHECK: liveins: $x0, $x1 25 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 26 ; CHECK: [[LOAD:%[0-9]+]]:_(s24) = G_LOAD [[COPY]](p0) :: (load 3 from %ir.ptr, align 1) 27 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s24) 28 ; CHECK: $w0 = COPY [[ZEXT]](s32) 29 ; CHECK: RET_ReallyLR implicit $w0 30 %0:_(p0) = COPY $x0 31 %1:_(p0) = COPY $x1 32 %2:_(s24) = G_LOAD %0(p0) :: (load 3 from %ir.ptr, align 1) 33 %3:_(s32) = G_ZEXT %2(s24) 34 $w0 = COPY %3(s32) 35 RET_ReallyLR implicit $w0 36 37... 38