1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s 3--- 4name: sextload_from_inreg 5alignment: 4 6tracksRegLiveness: true 7liveins: 8 - { reg: '$x0' } 9body: | 10 bb.1: 11 liveins: $x0 12 13 ; CHECK-LABEL: name: sextload_from_inreg 14 ; CHECK: liveins: $x0 15 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 16 ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load 1, align 2) 17 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16) 18 ; CHECK: $w0 = COPY [[ANYEXT]](s32) 19 ; CHECK: RET_ReallyLR implicit $w0 20 %0:_(p0) = COPY $x0 21 %1:_(s16) = G_LOAD %0(p0) :: (load 2) 22 %2:_(s16) = G_SEXT_INREG %1, 8 23 %3:_(s32) = G_ANYEXT %2(s16) 24 $w0 = COPY %3(s32) 25 RET_ReallyLR implicit $w0 26 27... 28--- 29name: non_pow_2_inreg 30alignment: 4 31tracksRegLiveness: true 32liveins: 33 - { reg: '$x0' } 34body: | 35 bb.1: 36 liveins: $x0 37 38 ; CHECK-LABEL: name: non_pow_2_inreg 39 ; CHECK: liveins: $x0 40 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 41 ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4) 42 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 24 43 ; CHECK: $w0 = COPY [[SEXT_INREG]](s32) 44 ; CHECK: RET_ReallyLR implicit $w0 45 %0:_(p0) = COPY $x0 46 %1:_(s32) = G_LOAD %0(p0) :: (load 4) 47 %2:_(s32) = G_SEXT_INREG %1, 24 48 $w0 = COPY %2(s32) 49 RET_ReallyLR implicit $w0 50 51... 52--- 53name: atomic 54alignment: 4 55tracksRegLiveness: true 56liveins: 57 - { reg: '$x0' } 58body: | 59 bb.1: 60 liveins: $x0 61 62 ; CHECK-LABEL: name: atomic 63 ; CHECK: liveins: $x0 64 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 65 ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load acquire 2) 66 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s16) = G_SEXT_INREG [[LOAD]], 8 67 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXT_INREG]](s16) 68 ; CHECK: $w0 = COPY [[ANYEXT]](s32) 69 ; CHECK: RET_ReallyLR implicit $w0 70 %0:_(p0) = COPY $x0 71 %1:_(s16) = G_LOAD %0(p0) :: (load acquire 2) 72 %2:_(s16) = G_SEXT_INREG %1, 8 73 %3:_(s32) = G_ANYEXT %2(s16) 74 $w0 = COPY %3(s32) 75 RET_ReallyLR implicit $w0 76 77... 78--- 79name: volatile 80alignment: 4 81tracksRegLiveness: true 82liveins: 83 - { reg: '$x0' } 84body: | 85 bb.1: 86 liveins: $x0 87 88 ; CHECK-LABEL: name: volatile 89 ; CHECK: liveins: $x0 90 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 91 ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (volatile load 2) 92 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s16) = G_SEXT_INREG [[LOAD]], 8 93 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXT_INREG]](s16) 94 ; CHECK: $w0 = COPY [[ANYEXT]](s32) 95 ; CHECK: RET_ReallyLR implicit $w0 96 %0:_(p0) = COPY $x0 97 %1:_(s16) = G_LOAD %0(p0) :: (volatile load 2) 98 %2:_(s16) = G_SEXT_INREG %1, 8 99 %3:_(s32) = G_ANYEXT %2(s16) 100 $w0 = COPY %3(s32) 101 RET_ReallyLR implicit $w0 102 103... 104