1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect -global-isel-abort=1 %s -o - | FileCheck %s 3 4name: v2s32_fpr 5alignment: 4 6legalized: true 7tracksRegLiveness: true 8registers: 9 - { id: 0, class: _ } 10 - { id: 1, class: _ } 11 - { id: 2, class: _ } 12body: | 13 bb.1.entry: 14 liveins: $d0 15 16 %0:_(<2 x s32>) = COPY $d0 17 %2:_(s64) = G_CONSTANT i64 1 18 %1:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %2(s64) 19 $s0 = COPY %1(s32) 20 RET_ReallyLR implicit $s0 21 22... 23--- 24name: v4s32_gpr 25alignment: 4 26legalized: true 27tracksRegLiveness: true 28registers: 29 - { id: 0, class: _ } 30 - { id: 1, class: _ } 31 - { id: 2, class: _ } 32body: | 33 bb.1.entry: 34 liveins: $q0 35 36 ; CHECK-LABEL: name: v4s32_gpr 37 ; CHECK: liveins: $q0 38 ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0 39 ; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0 40 ; CHECK: [[EVEC:%[0-9]+]]:fpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s64) 41 ; CHECK: $s0 = COPY [[EVEC]](s32) 42 ; CHECK: RET_ReallyLR implicit $s0 43 %0:_(<4 x s32>) = COPY $q0 44 %2:_(s64) = G_CONSTANT i64 0 45 %1:_(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %2(s64) 46 $s0 = COPY %1(s32) 47 RET_ReallyLR implicit $s0 48 49... 50--- 51name: v2s64_fpr 52alignment: 4 53legalized: true 54tracksRegLiveness: true 55registers: 56 - { id: 0, class: _ } 57 - { id: 1, class: _ } 58 - { id: 2, class: _ } 59body: | 60 bb.1.entry: 61 liveins: $q0 62 63 ; CHECK-LABEL: name: v2s64_fpr 64 ; CHECK: liveins: $q0 65 ; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0 66 ; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 2 67 ; CHECK: [[EVEC:%[0-9]+]]:fpr(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](s64) 68 ; CHECK: $d0 = COPY [[EVEC]](s64) 69 ; CHECK: RET_ReallyLR implicit $d0 70 %0:_(<2 x s64>) = COPY $q0 71 %2:_(s64) = G_CONSTANT i64 2 72 %1:_(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %2(s64) 73 $d0 = COPY %1(s64) 74 RET_ReallyLR implicit $d0 75 76... 77--- 78name: v4s16_fpr 79alignment: 4 80legalized: true 81tracksRegLiveness: true 82registers: 83 - { id: 0, class: _ } 84 - { id: 1, class: _ } 85 - { id: 2, class: _ } 86body: | 87 bb.1.entry: 88 liveins: $d0 89 90 ; CHECK-LABEL: name: v4s16_fpr 91 ; CHECK: liveins: $d0 92 ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s16>) = COPY $d0 93 ; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 94 ; CHECK: [[EVEC:%[0-9]+]]:fpr(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s16>), [[C]](s64) 95 ; CHECK: $h0 = COPY [[EVEC]](s16) 96 ; CHECK: RET_ReallyLR implicit $h0 97 %0:_(<4 x s16>) = COPY $d0 98 %2:_(s64) = G_CONSTANT i64 1 99 %1:_(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %2(s64) 100 $h0 = COPY %1(s16) 101 RET_ReallyLR implicit $h0 102 103... 104