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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect %s -o - | FileCheck %s
3
4# The following should hold here:
5#
6# 1) The first and second operands of G_INSERT_VECTOR_ELT should be FPRs since
7#    they are vectors.
8#
9# 2) The third operand should be on the register bank given in the test name
10#    (e.g, v4s32_fpr). AArch64 supports native inserts of GPRs, so we need to
11#    preserve that.
12#
13# 3) The fourth operand should be a GPR, since it's a constant.
14
15name:            v4s32_fpr
16alignment:       4
17legalized:       true
18tracksRegLiveness: true
19body:             |
20  bb.0:
21    liveins: $q1, $s0
22
23    ; CHECK-LABEL: name: v4s32_fpr
24    ; CHECK: liveins: $q1, $s0
25    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
26    ; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q1
27    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
28    ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32)
29    ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
30    ; CHECK: RET_ReallyLR implicit $q0
31    %0:_(s32) = COPY $s0
32    %1:_(<4 x s32>) = COPY $q1
33    %3:_(s32) = G_CONSTANT i32 1
34    %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
35    $q0 = COPY %2(<4 x s32>)
36    RET_ReallyLR implicit $q0
37
38...
39---
40name:            v4s32_gpr
41alignment:       4
42legalized:       true
43tracksRegLiveness: true
44body:             |
45  bb.0:
46    liveins: $q0, $w0
47
48    ; CHECK-LABEL: name: v4s32_gpr
49    ; CHECK: liveins: $q0, $w0
50    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
51    ; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
52    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
53    ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32)
54    ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
55    ; CHECK: RET_ReallyLR implicit $q0
56    %0:_(s32) = COPY $w0
57    %1:_(<4 x s32>) = COPY $q0
58    %3:_(s32) = G_CONSTANT i32 1
59    %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
60    $q0 = COPY %2(<4 x s32>)
61    RET_ReallyLR implicit $q0
62
63...
64---
65name:            v2s64_fpr
66alignment:       4
67legalized:       true
68tracksRegLiveness: true
69body:             |
70  bb.0:
71    liveins: $d0, $q1
72
73    ; CHECK-LABEL: name: v2s64_fpr
74    ; CHECK: liveins: $d0, $q1
75    ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
76    ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q1
77    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
78    ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s32)
79    ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>)
80    ; CHECK: RET_ReallyLR implicit $q0
81    %0:_(s64) = COPY $d0
82    %1:_(<2 x s64>) = COPY $q1
83    %3:_(s32) = G_CONSTANT i32 1
84    %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
85    $q0 = COPY %2(<2 x s64>)
86    RET_ReallyLR implicit $q0
87
88...
89---
90name:            v2s64_gpr
91alignment:       4
92legalized:       true
93tracksRegLiveness: true
94body:             |
95  bb.0:
96    liveins: $q0, $x0
97
98    ; CHECK-LABEL: name: v2s64_gpr
99    ; CHECK: liveins: $q0, $x0
100    ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
101    ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
102    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
103    ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s32)
104    ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>)
105    ; CHECK: RET_ReallyLR implicit $q0
106    %0:_(s64) = COPY $x0
107    %1:_(<2 x s64>) = COPY $q0
108    %3:_(s32) = G_CONSTANT i32 0
109    %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
110    $q0 = COPY %2(<2 x s64>)
111    RET_ReallyLR implicit $q0
112
113...
114---
115name:            v2s32_fpr
116alignment:       4
117legalized:       true
118tracksRegLiveness: true
119body:             |
120  bb.0:
121    liveins: $d1, $s0
122
123    ; CHECK-LABEL: name: v2s32_fpr
124    ; CHECK: liveins: $d1, $s0
125    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
126    ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d1
127    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
128    ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32)
129    ; CHECK: $d0 = COPY [[IVEC]](<2 x s32>)
130    ; CHECK: RET_ReallyLR implicit $d0
131    %0:_(s32) = COPY $s0
132    %1:_(<2 x s32>) = COPY $d1
133    %3:_(s32) = G_CONSTANT i32 1
134    %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
135    $d0 = COPY %2(<2 x s32>)
136    RET_ReallyLR implicit $d0
137
138...
139---
140name:            v2s32_gpr
141alignment:       4
142legalized:       true
143tracksRegLiveness: true
144body:             |
145  bb.0:
146    liveins: $d0, $w0
147
148    ; CHECK-LABEL: name: v2s32_gpr
149    ; CHECK: liveins: $d0, $w0
150    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
151    ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0
152    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
153    ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32)
154    ; CHECK: $d0 = COPY [[IVEC]](<2 x s32>)
155    ; CHECK: RET_ReallyLR implicit $d0
156    %0:_(s32) = COPY $w0
157    %1:_(<2 x s32>) = COPY $d0
158    %3:_(s32) = G_CONSTANT i32 1
159    %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
160    $d0 = COPY %2(<2 x s32>)
161    RET_ReallyLR implicit $d0
162
163...
164