1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3# Verify that we get FCMPSri when we compare against 0.0 and that we get 4# FCMPSrr otherwise. 5 6... 7--- 8name: zero 9alignment: 4 10legalized: true 11regBankSelected: true 12tracksRegLiveness: true 13body: | 14 bb.1: 15 liveins: $s0, $s1 16 17 ; CHECK-LABEL: name: zero 18 ; CHECK: liveins: $s0, $s1 19 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 20 ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv 21 ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 22 ; CHECK: $s0 = COPY [[CSINCWr]] 23 ; CHECK: RET_ReallyLR implicit $s0 24 %0:fpr(s32) = COPY $s0 25 %1:fpr(s32) = COPY $s1 26 %2:fpr(s32) = G_FCONSTANT float 0.000000e+00 27 %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2 28 $s0 = COPY %3(s32) 29 RET_ReallyLR implicit $s0 30 31... 32--- 33name: notzero 34alignment: 4 35legalized: true 36regBankSelected: true 37tracksRegLiveness: true 38machineFunctionInfo: {} 39body: | 40 bb.1: 41 liveins: $s0, $s1 42 43 ; CHECK-LABEL: name: notzero 44 ; CHECK: liveins: $s0, $s1 45 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 46 ; CHECK: [[FMOVSi:%[0-9]+]]:fpr32 = FMOVSi 112 47 ; CHECK: FCMPSrr [[COPY]], [[FMOVSi]], implicit-def $nzcv 48 ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 49 ; CHECK: $s0 = COPY [[CSINCWr]] 50 ; CHECK: RET_ReallyLR implicit $s0 51 %0:fpr(s32) = COPY $s0 52 %1:fpr(s32) = COPY $s1 53 %2:fpr(s32) = G_FCONSTANT float 1.000000e+00 54 %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2 55 $s0 = COPY %3(s32) 56 RET_ReallyLR implicit $s0 57 58... 59--- 60name: notzero_s64 61alignment: 4 62legalized: true 63regBankSelected: true 64tracksRegLiveness: true 65machineFunctionInfo: {} 66body: | 67 bb.1: 68 liveins: $d0, $d1 69 70 ; CHECK-LABEL: name: notzero_s64 71 ; CHECK: liveins: $d0, $d1 72 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 73 ; CHECK: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 112 74 ; CHECK: FCMPDrr [[COPY]], [[FMOVDi]], implicit-def $nzcv 75 ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 76 ; CHECK: $s0 = COPY [[CSINCWr]] 77 ; CHECK: RET_ReallyLR implicit $s0 78 %0:fpr(s64) = COPY $d0 79 %1:fpr(s64) = COPY $d1 80 %2:fpr(s64) = G_FCONSTANT double 1.000000e+00 81 %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2 82 $s0 = COPY %3(s32) 83 RET_ReallyLR implicit $s0 84 85 86... 87--- 88name: zero_s64 89alignment: 4 90legalized: true 91regBankSelected: true 92tracksRegLiveness: true 93body: | 94 bb.1: 95 liveins: $d0, $d1, $s0 96 97 ; CHECK-LABEL: name: zero_s64 98 ; CHECK: liveins: $d0, $d1, $s0 99 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 100 ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv 101 ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 102 ; CHECK: $s0 = COPY [[CSINCWr]] 103 ; CHECK: RET_ReallyLR implicit $s0 104 %0:fpr(s64) = COPY $d0 105 %1:fpr(s64) = COPY $d1 106 %2:fpr(s64) = G_FCONSTANT double 0.000000e+00 107 %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2 108 $s0 = COPY %3(s32) 109 RET_ReallyLR implicit $s0 110