1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s 3--- 4name: shl_cimm_32 5legalized: true 6regBankSelected: true 7body: | 8 bb.1: 9 liveins: $w0 10 11 ; CHECK-LABEL: name: shl_cimm_32 12 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 13 ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 24, 23 14 ; CHECK: $w0 = COPY [[UBFMWri]] 15 ; CHECK: RET_ReallyLR implicit $w0 16 %0:gpr(s32) = COPY $w0 17 %1:gpr(s32) = G_CONSTANT i32 8 18 %2:gpr(s32) = G_SHL %0, %1(s32) 19 $w0 = COPY %2(s32) 20 RET_ReallyLR implicit $w0 21 22... 23--- 24name: shl_cimm_64 25legalized: true 26regBankSelected: true 27body: | 28 bb.1: 29 liveins: $x0 30 31 ; CHECK-LABEL: name: shl_cimm_64 32 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 33 ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 56, 55 34 ; CHECK: $x0 = COPY [[UBFMXri]] 35 ; CHECK: RET_ReallyLR implicit $x0 36 %0:gpr(s64) = COPY $x0 37 %1:gpr(s64) = G_CONSTANT i64 8 38 %2:gpr(s64) = G_SHL %0, %1(s64) 39 $x0 = COPY %2(s64) 40 RET_ReallyLR implicit $x0 41 42... 43--- 44name: lshr_cimm_32 45legalized: true 46regBankSelected: true 47body: | 48 bb.1: 49 liveins: $w0 50 51 ; CHECK-LABEL: name: lshr_cimm_32 52 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 53 ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 8, 31 54 ; CHECK: $w0 = COPY [[UBFMWri]] 55 ; CHECK: RET_ReallyLR implicit $w0 56 %0:gpr(s32) = COPY $w0 57 %3:gpr(s64) = G_CONSTANT i64 8 58 %2:gpr(s32) = G_LSHR %0, %3(s64) 59 $w0 = COPY %2(s32) 60 RET_ReallyLR implicit $w0 61 62... 63--- 64name: lshr_cimm_64 65legalized: true 66regBankSelected: true 67body: | 68 bb.1: 69 liveins: $x0 70 71 ; CHECK-LABEL: name: lshr_cimm_64 72 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 73 ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 8, 63 74 ; CHECK: $x0 = COPY [[UBFMXri]] 75 ; CHECK: RET_ReallyLR implicit $x0 76 %0:gpr(s64) = COPY $x0 77 %1:gpr(s64) = G_CONSTANT i64 8 78 %2:gpr(s64) = G_LSHR %0, %1(s64) 79 $x0 = COPY %2(s64) 80 RET_ReallyLR implicit $x0 81 82... 83--- 84name: ashr_cimm_32 85legalized: true 86regBankSelected: true 87body: | 88 bb.1: 89 liveins: $w0 90 91 ; CHECK-LABEL: name: ashr_cimm_32 92 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 93 ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 8, 31 94 ; CHECK: $w0 = COPY [[SBFMWri]] 95 ; CHECK: RET_ReallyLR implicit $w0 96 %0:gpr(s32) = COPY $w0 97 %3:gpr(s64) = G_CONSTANT i64 8 98 %2:gpr(s32) = G_ASHR %0, %3(s64) 99 $w0 = COPY %2(s32) 100 RET_ReallyLR implicit $w0 101 102... 103--- 104name: ashr_cimm_64 105legalized: true 106regBankSelected: true 107body: | 108 bb.1: 109 liveins: $x0 110 111 ; CHECK-LABEL: name: ashr_cimm_64 112 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 113 ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[COPY]], 8, 63 114 ; CHECK: $x0 = COPY [[SBFMXri]] 115 ; CHECK: RET_ReallyLR implicit $x0 116 %0:gpr(s64) = COPY $x0 117 %1:gpr(s64) = G_CONSTANT i64 8 118 %2:gpr(s64) = G_ASHR %0, %1(s64) 119 $x0 = COPY %2(s64) 120 RET_ReallyLR implicit $x0 121 122... 123--- 124name: lshr_32_notimm64 125legalized: true 126regBankSelected: true 127body: | 128 bb.1: 129 liveins: $w0 130 131 ; CHECK-LABEL: name: lshr_32_notimm64 132 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 133 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8 134 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 135 ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[SUBREG_TO_REG]], 8000 136 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32 137 ; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]] 138 ; CHECK: $w0 = COPY [[LSRVWr]] 139 ; CHECK: RET_ReallyLR implicit $w0 140 %0:gpr(s32) = COPY $w0 141 %3:gpr(s64) = G_CONSTANT i64 8 142 %4:gpr(s64) = G_AND %3, %3 143 %2:gpr(s32) = G_LSHR %0, %4(s64) 144 $w0 = COPY %2(s32) 145 RET_ReallyLR implicit $w0 146 147... 148--- 149name: ashr_32_notimm64 150legalized: true 151regBankSelected: true 152body: | 153 bb.1: 154 liveins: $w0 155 156 ; CHECK-LABEL: name: ashr_32_notimm64 157 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 158 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8 159 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 160 ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[SUBREG_TO_REG]], 8000 161 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32 162 ; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]] 163 ; CHECK: $w0 = COPY [[ASRVWr]] 164 ; CHECK: RET_ReallyLR implicit $w0 165 %0:gpr(s32) = COPY $w0 166 %3:gpr(s64) = G_CONSTANT i64 8 167 %4:gpr(s64) = G_AND %3, %3 168 %2:gpr(s32) = G_ASHR %0, %4(s64) 169 $w0 = COPY %2(s32) 170 RET_ReallyLR implicit $w0 171 172... 173