1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3--- | 4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 5 target triple = "aarch64" 6 7 @x = global i32 -32768, align 4 8 9 define i32 @check_sext_not_lost(i32* %ptr) { 10 entry: 11 %ptr.addr = alloca i32*, align 8 12 store i32* %ptr, i32** %ptr.addr, align 8 13 %0 = load i32*, i32** %ptr.addr, align 8 14 %1 = load i32, i32* @x, align 4 15 %sub = sub nsw i32 %1, 32768 16 %conv = trunc i32 %sub to i16 17 %idxprom = sext i16 %conv to i64 18 %arrayidx = getelementptr inbounds i32, i32* %0, i64 %idxprom 19 %2 = load i32, i32* %arrayidx, align 4 20 ret i32 %2 21 } 22 23... 24--- 25name: check_sext_not_lost 26alignment: 4 27legalized: true 28regBankSelected: true 29tracksRegLiveness: true 30registers: 31 - { id: 0, class: gpr } 32 - { id: 1, class: gpr } 33 - { id: 2, class: gpr } 34 - { id: 3, class: gpr } 35 - { id: 4, class: gpr } 36 - { id: 5, class: gpr } 37 - { id: 6, class: gpr } 38 - { id: 7, class: _ } 39 - { id: 8, class: gpr } 40 - { id: 9, class: _ } 41 - { id: 10, class: gpr } 42 - { id: 11, class: gpr } 43 - { id: 12, class: _ } 44 - { id: 13, class: gpr } 45 - { id: 14, class: gpr } 46 - { id: 15, class: gpr64 } 47 - { id: 16, class: gpr } 48liveins: 49 - { reg: '$x0' } 50frameInfo: 51 maxAlignment: 8 52 maxCallFrameSize: 0 53stack: 54 - { id: 0, name: ptr.addr, size: 8, alignment: 8 } 55machineFunctionInfo: {} 56body: | 57 bb.0.entry: 58 liveins: $x0 59 60 ; CHECK-LABEL: name: check_sext_not_lost 61 ; CHECK: liveins: $x0 62 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 63 ; CHECK: STRXui [[COPY]], %stack.0.ptr.addr, 0 :: (store 8 into %ir.ptr.addr) 64 ; CHECK: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui %stack.0.ptr.addr, 0 :: (dereferenceable load 8 from %ir.ptr.addr) 65 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @x 66 ; CHECK: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @x :: (dereferenceable load 4 from @x) 67 ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = nsw SUBSWri [[LDRWui]], 8, 12, implicit-def $nzcv 68 ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF 69 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[SUBSWri]], %subreg.sub_32 70 ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 15 71 ; CHECK: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[LDRXui]], [[SBFMXri]], 0, 1 :: (load 4 from %ir.arrayidx) 72 ; CHECK: $w0 = COPY [[LDRWroX]] 73 ; CHECK: RET_ReallyLR implicit $w0 74 %0:gpr(p0) = COPY $x0 75 %1:gpr(p0) = G_FRAME_INDEX %stack.0.ptr.addr 76 G_STORE %0(p0), %1(p0) :: (store 8 into %ir.ptr.addr) 77 %2:gpr(p0) = G_LOAD %1(p0) :: (dereferenceable load 8 from %ir.ptr.addr) 78 %15:gpr64(p0) = ADRP target-flags(aarch64-page) @x 79 %4:gpr(p0) = G_ADD_LOW %15(p0), target-flags(aarch64-pageoff, aarch64-nc) @x 80 %3:gpr(s32) = G_LOAD %4(p0) :: (dereferenceable load 4 from @x) 81 %5:gpr(s32) = G_CONSTANT i32 32768 82 %6:gpr(s32) = nsw G_SUB %3, %5 83 %16:gpr(s64) = G_ANYEXT %6(s32) 84 %8:gpr(s64) = G_SEXT_INREG %16, 16 85 %14:gpr(s64) = G_CONSTANT i64 2 86 %10:gpr(s64) = G_SHL %8, %14(s64) 87 %11:gpr(p0) = G_PTR_ADD %2, %10(s64) 88 %13:gpr(s32) = G_LOAD %11(p0) :: (load 4 from %ir.arrayidx) 89 $w0 = COPY %13(s32) 90 RET_ReallyLR implicit $w0 91 92... 93