1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o -| FileCheck %s 3 4define i64 @umull(i64 %x0, i64 %x1) { 5; CHECK-LABEL: umull: 6; CHECK: // %bb.0: // %entry 7; CHECK-NEXT: umull x0, w1, w0 8; CHECK-NEXT: ret 9entry: 10 %and = and i64 %x0, 4294967295 11 %and1 = and i64 %x1, 4294967295 12 %mul = mul nuw i64 %and1, %and 13 ret i64 %mul 14} 15 16define i64 @umull2(i64 %x, i32 %y) { 17; CHECK-LABEL: umull2: 18; CHECK: // %bb.0: // %entry 19; CHECK-NEXT: umull x0, w0, w1 20; CHECK-NEXT: ret 21entry: 22 %and = and i64 %x, 4294967295 23 %conv = zext i32 %y to i64 24 %mul = mul nuw nsw i64 %and, %conv 25 ret i64 %mul 26} 27 28define i64 @umull2_commuted(i64 %x, i32 %y) { 29; CHECK-LABEL: umull2_commuted: 30; CHECK: // %bb.0: // %entry 31; CHECK-NEXT: umull x0, w0, w1 32; CHECK-NEXT: ret 33entry: 34 %and = and i64 %x, 4294967295 35 %conv = zext i32 %y to i64 36 %mul = mul nuw nsw i64 %conv, %and 37 ret i64 %mul 38} 39 40define i64 @smull(i64 %x0, i64 %x1) { 41; CHECK-LABEL: smull: 42; CHECK: // %bb.0: // %entry 43; CHECK-NEXT: smull x0, w1, w0 44; CHECK-NEXT: ret 45entry: 46 %sext = shl i64 %x0, 32 47 %conv1 = ashr exact i64 %sext, 32 48 %sext4 = shl i64 %x1, 32 49 %conv3 = ashr exact i64 %sext4, 32 50 %mul = mul nsw i64 %conv3, %conv1 51 ret i64 %mul 52} 53 54define i64 @smull2(i64 %x, i32 %y) { 55; CHECK-LABEL: smull2: 56; CHECK: // %bb.0: // %entry 57; CHECK-NEXT: smull x0, w0, w1 58; CHECK-NEXT: ret 59entry: 60 %shl = shl i64 %x, 32 61 %shr = ashr exact i64 %shl, 32 62 %conv = sext i32 %y to i64 63 %mul = mul nsw i64 %shr, %conv 64 ret i64 %mul 65} 66 67define i64 @smull2_commuted(i64 %x, i32 %y) { 68; CHECK-LABEL: smull2_commuted: 69; CHECK: // %bb.0: // %entry 70; CHECK-NEXT: smull x0, w0, w1 71; CHECK-NEXT: ret 72entry: 73 %shl = shl i64 %x, 32 74 %shr = ashr exact i64 %shl, 32 75 %conv = sext i32 %y to i64 76 %mul = mul nsw i64 %conv, %shr 77 ret i64 %mul 78} 79