1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone -mattr=+slow-misaligned-128store | FileCheck %s 2%struct.X = type <{ i32, i64, i64 }> 3 4define void @foo1(i32* %p, i64 %val) nounwind { 5; CHECK-LABEL: foo1: 6; CHECK: stur w1, [x0, #-4] 7; CHECK-NEXT: ret 8 %tmp1 = trunc i64 %val to i32 9 %ptr = getelementptr inbounds i32, i32* %p, i64 -1 10 store i32 %tmp1, i32* %ptr, align 4 11 ret void 12} 13define void @foo2(i16* %p, i64 %val) nounwind { 14; CHECK-LABEL: foo2: 15; CHECK: sturh w1, [x0, #-2] 16; CHECK-NEXT: ret 17 %tmp1 = trunc i64 %val to i16 18 %ptr = getelementptr inbounds i16, i16* %p, i64 -1 19 store i16 %tmp1, i16* %ptr, align 2 20 ret void 21} 22define void @foo3(i8* %p, i64 %val) nounwind { 23; CHECK-LABEL: foo3: 24; CHECK: sturb w1, [x0, #-1] 25; CHECK-NEXT: ret 26 %tmp1 = trunc i64 %val to i8 27 %ptr = getelementptr inbounds i8, i8* %p, i64 -1 28 store i8 %tmp1, i8* %ptr, align 1 29 ret void 30} 31define void @foo4(i16* %p, i32 %val) nounwind { 32; CHECK-LABEL: foo4: 33; CHECK: sturh w1, [x0, #-2] 34; CHECK-NEXT: ret 35 %tmp1 = trunc i32 %val to i16 36 %ptr = getelementptr inbounds i16, i16* %p, i32 -1 37 store i16 %tmp1, i16* %ptr, align 2 38 ret void 39} 40define void @foo5(i8* %p, i32 %val) nounwind { 41; CHECK-LABEL: foo5: 42; CHECK: sturb w1, [x0, #-1] 43; CHECK-NEXT: ret 44 %tmp1 = trunc i32 %val to i8 45 %ptr = getelementptr inbounds i8, i8* %p, i32 -1 46 store i8 %tmp1, i8* %ptr, align 1 47 ret void 48} 49 50define void @foo(%struct.X* nocapture %p) nounwind optsize ssp { 51; CHECK-LABEL: foo: 52; CHECK-NOT: str 53; CHECK: stur xzr, [x0, #12] 54; CHECK-NEXT: stur xzr, [x0, #4] 55; CHECK-NEXT: ret 56 %B = getelementptr inbounds %struct.X, %struct.X* %p, i64 0, i32 1 57 %val = bitcast i64* %B to i8* 58 call void @llvm.memset.p0i8.i64(i8* %val, i8 0, i64 16, i1 false) 59 ret void 60} 61 62declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind 63 64; Unaligned 16b stores are split into 8b stores for performance. 65; radar://15424193 66 67; CHECK-LABEL: unaligned: 68; CHECK-NOT: str q0 69; CHECK: str d[[REG:[0-9]+]], [x0] 70; CHECK: ext.16b v[[REG2:[0-9]+]], v[[REG]], v[[REG]], #8 71; CHECK: str d[[REG2]], [x0, #8] 72define void @unaligned(<4 x i32>* %p, <4 x i32> %v) nounwind { 73 store <4 x i32> %v, <4 x i32>* %p, align 4 74 ret void 75} 76 77; CHECK-LABEL: aligned: 78; CHECK: str q0 79define void @aligned(<4 x i32>* %p, <4 x i32> %v) nounwind { 80 store <4 x i32> %v, <4 x i32>* %p 81 ret void 82} 83 84; Don't split one and two byte aligned stores. 85; radar://16349308 86 87; CHECK-LABEL: twobytealign: 88; CHECK: str q0 89define void @twobytealign(<4 x i32>* %p, <4 x i32> %v) nounwind { 90 store <4 x i32> %v, <4 x i32>* %p, align 2 91 ret void 92} 93; CHECK-LABEL: onebytealign: 94; CHECK: str q0 95define void @onebytealign(<4 x i32>* %p, <4 x i32> %v) nounwind { 96 store <4 x i32> %v, <4 x i32>* %p, align 1 97 ret void 98} 99