1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s 2; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* 2>&1 | FileCheck %s --check-prefixes=CHECK,FALLBACK 3 4; Test efficient codegen of vector extends up from legal type to 128 bit 5; and 256 bit vector types. 6 7;----- 8; Vectors of i16. 9;----- 10 11; FALLBACK-NOT: remark:{{.*}}(in function: func1) 12define <8 x i16> @func1(<8 x i8> %v0) nounwind { 13; CHECK-LABEL: func1: 14; CHECK-NEXT: ushll.8h v0, v0, #0 15; CHECK-NEXT: ret 16 %r = zext <8 x i8> %v0 to <8 x i16> 17 ret <8 x i16> %r 18} 19 20; FALLBACK-NOT: remark:{{.*}}(in function: func2) 21define <8 x i16> @func2(<8 x i8> %v0) nounwind { 22; CHECK-LABEL: func2: 23; CHECK-NEXT: sshll.8h v0, v0, #0 24; CHECK-NEXT: ret 25 %r = sext <8 x i8> %v0 to <8 x i16> 26 ret <8 x i16> %r 27} 28 29define <16 x i16> @func3(<16 x i8> %v0) nounwind { 30; CHECK-LABEL: func3: 31; CHECK-NEXT: ushll2.8h v1, v0, #0 32; CHECK-NEXT: ushll.8h v0, v0, #0 33; CHECK-NEXT: ret 34 %r = zext <16 x i8> %v0 to <16 x i16> 35 ret <16 x i16> %r 36} 37 38define <16 x i16> @func4(<16 x i8> %v0) nounwind { 39; CHECK-LABEL: func4: 40; CHECK-NEXT: sshll2.8h v1, v0, #0 41; CHECK-NEXT: sshll.8h v0, v0, #0 42; CHECK-NEXT: ret 43 %r = sext <16 x i8> %v0 to <16 x i16> 44 ret <16 x i16> %r 45} 46 47;----- 48; Vectors of i32. 49;----- 50 51; FALLBACK-NOT: remark:{{.*}}(in function: afunc1) 52define <4 x i32> @afunc1(<4 x i16> %v0) nounwind { 53; CHECK-LABEL: afunc1: 54; CHECK-NEXT: ushll.4s v0, v0, #0 55; CHECK-NEXT: ret 56 %r = zext <4 x i16> %v0 to <4 x i32> 57 ret <4 x i32> %r 58} 59 60; FALLBACK-NOT: remark:{{.*}}(in function: afunc2) 61define <4 x i32> @afunc2(<4 x i16> %v0) nounwind { 62; CHECK-LABEL: afunc2: 63; CHECK-NEXT: sshll.4s v0, v0, #0 64; CHECK-NEXT: ret 65 %r = sext <4 x i16> %v0 to <4 x i32> 66 ret <4 x i32> %r 67} 68 69define <8 x i32> @afunc3(<8 x i16> %v0) nounwind { 70; CHECK-LABEL: afunc3: 71; CHECK-NEXT: ushll2.4s v1, v0, #0 72; CHECK-NEXT: ushll.4s v0, v0, #0 73; CHECK-NEXT: ret 74 %r = zext <8 x i16> %v0 to <8 x i32> 75 ret <8 x i32> %r 76} 77 78define <8 x i32> @afunc4(<8 x i16> %v0) nounwind { 79; CHECK-LABEL: afunc4: 80; CHECK-NEXT: sshll2.4s v1, v0, #0 81; CHECK-NEXT: sshll.4s v0, v0, #0 82; CHECK-NEXT: ret 83 %r = sext <8 x i16> %v0 to <8 x i32> 84 ret <8 x i32> %r 85} 86 87define <8 x i32> @bfunc1(<8 x i8> %v0) nounwind { 88; CHECK-LABEL: bfunc1: 89; CHECK-NEXT: ushll.8h v0, v0, #0 90; CHECK-NEXT: ushll2.4s v1, v0, #0 91; CHECK-NEXT: ushll.4s v0, v0, #0 92; CHECK-NEXT: ret 93 %r = zext <8 x i8> %v0 to <8 x i32> 94 ret <8 x i32> %r 95} 96 97define <8 x i32> @bfunc2(<8 x i8> %v0) nounwind { 98; CHECK-LABEL: bfunc2: 99; CHECK-NEXT: sshll.8h v0, v0, #0 100; CHECK-NEXT: sshll2.4s v1, v0, #0 101; CHECK-NEXT: sshll.4s v0, v0, #0 102; CHECK-NEXT: ret 103 %r = sext <8 x i8> %v0 to <8 x i32> 104 ret <8 x i32> %r 105} 106 107;----- 108; Vectors of i64. 109;----- 110 111define <4 x i64> @zfunc1(<4 x i32> %v0) nounwind { 112; CHECK-LABEL: zfunc1: 113; CHECK-NEXT: ushll2.2d v1, v0, #0 114; CHECK-NEXT: ushll.2d v0, v0, #0 115; CHECK-NEXT: ret 116 %r = zext <4 x i32> %v0 to <4 x i64> 117 ret <4 x i64> %r 118} 119 120define <4 x i64> @zfunc2(<4 x i32> %v0) nounwind { 121; CHECK-LABEL: zfunc2: 122; CHECK-NEXT: sshll2.2d v1, v0, #0 123; CHECK-NEXT: sshll.2d v0, v0, #0 124; CHECK-NEXT: ret 125 %r = sext <4 x i32> %v0 to <4 x i64> 126 ret <4 x i64> %r 127} 128 129define <4 x i64> @bfunc3(<4 x i16> %v0) nounwind { 130; CHECK-LABEL: func3: 131; CHECK-NEXT: ushll.4s v0, v0, #0 132; CHECK-NEXT: ushll2.2d v1, v0, #0 133; CHECK-NEXT: ushll.2d v0, v0, #0 134; CHECK-NEXT: ret 135 %r = zext <4 x i16> %v0 to <4 x i64> 136 ret <4 x i64> %r 137} 138 139define <4 x i64> @cfunc4(<4 x i16> %v0) nounwind { 140; CHECK-LABEL: func4: 141; CHECK-NEXT: sshll.4s v0, v0, #0 142; CHECK-NEXT: sshll2.2d v1, v0, #0 143; CHECK-NEXT: sshll.2d v0, v0, #0 144; CHECK-NEXT: ret 145 %r = sext <4 x i16> %v0 to <4 x i64> 146 ret <4 x i64> %r 147} 148