1; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-none-eabi -mattr=+bf16 | FileCheck %s 2 3define <4 x i16> @v4bf16_to_v4i16(float, <4 x bfloat> %a) nounwind { 4; CHECK-LABEL: v4bf16_to_v4i16: 5; CHECK-NEXT: mov v0.16b, v1.16b 6; CHECK-NEXT: ret 7entry: 8 %1 = bitcast <4 x bfloat> %a to <4 x i16> 9 ret <4 x i16> %1 10} 11 12define <2 x i32> @v4bf16_to_v2i32(float, <4 x bfloat> %a) nounwind { 13; CHECK-LABEL: v4bf16_to_v2i32: 14; CHECK-NEXT: mov v0.16b, v1.16b 15; CHECK-NEXT: ret 16entry: 17 %1 = bitcast <4 x bfloat> %a to <2 x i32> 18 ret <2 x i32> %1 19} 20 21define <1 x i64> @v4bf16_to_v1i64(float, <4 x bfloat> %a) nounwind { 22; CHECK-LABEL: v4bf16_to_v1i64: 23; CHECK-NEXT: mov v0.16b, v1.16b 24; CHECK-NEXT: ret 25entry: 26 %1 = bitcast <4 x bfloat> %a to <1 x i64> 27 ret <1 x i64> %1 28} 29 30define i64 @v4bf16_to_i64(float, <4 x bfloat> %a) nounwind { 31; CHECK-LABEL: v4bf16_to_i64: 32; CHECK-NEXT: fmov x0, d1 33; CHECK-NEXT: ret 34entry: 35 %1 = bitcast <4 x bfloat> %a to i64 36 ret i64 %1 37} 38 39define <2 x float> @v4bf16_to_v2float(float, <4 x bfloat> %a) nounwind { 40; CHECK-LABEL: v4bf16_to_v2float: 41; CHECK-NEXT: mov v0.16b, v1.16b 42; CHECK-NEXT: ret 43entry: 44 %1 = bitcast <4 x bfloat> %a to <2 x float> 45 ret <2 x float> %1 46} 47 48define <1 x double> @v4bf16_to_v1double(float, <4 x bfloat> %a) nounwind { 49; CHECK-LABEL: v4bf16_to_v1double: 50; CHECK-NEXT: mov v0.16b, v1.16b 51; CHECK-NEXT: ret 52entry: 53 %1 = bitcast <4 x bfloat> %a to <1 x double> 54 ret <1 x double> %1 55} 56 57define double @v4bf16_to_double(float, <4 x bfloat> %a) nounwind { 58; CHECK-LABEL: v4bf16_to_double: 59; CHECK-NEXT: mov v0.16b, v1.16b 60; CHECK-NEXT: ret 61entry: 62 %1 = bitcast <4 x bfloat> %a to double 63 ret double %1 64} 65 66 67define <4 x bfloat> @v4i16_to_v4bf16(float, <4 x i16> %a) nounwind { 68; CHECK-LABEL: v4i16_to_v4bf16: 69; CHECK-NEXT: mov v0.16b, v1.16b 70; CHECK-NEXT: ret 71entry: 72 %1 = bitcast <4 x i16> %a to <4 x bfloat> 73 ret <4 x bfloat> %1 74} 75 76define <4 x bfloat> @v2i32_to_v4bf16(float, <2 x i32> %a) nounwind { 77; CHECK-LABEL: v2i32_to_v4bf16: 78; CHECK-NEXT: mov v0.16b, v1.16b 79; CHECK-NEXT: ret 80entry: 81 %1 = bitcast <2 x i32> %a to <4 x bfloat> 82 ret <4 x bfloat> %1 83} 84 85define <4 x bfloat> @v1i64_to_v4bf16(float, <1 x i64> %a) nounwind { 86; CHECK-LABEL: v1i64_to_v4bf16: 87; CHECK-NEXT: mov v0.16b, v1.16b 88; CHECK-NEXT: ret 89entry: 90 %1 = bitcast <1 x i64> %a to <4 x bfloat> 91 ret <4 x bfloat> %1 92} 93 94define <4 x bfloat> @i64_to_v4bf16(float, i64 %a) nounwind { 95; CHECK-LABEL: i64_to_v4bf16: 96; CHECK-NEXT: fmov d0, x0 97; CHECK-NEXT: ret 98entry: 99 %1 = bitcast i64 %a to <4 x bfloat> 100 ret <4 x bfloat> %1 101} 102 103define <4 x bfloat> @v2float_to_v4bf16(float, <2 x float> %a) nounwind { 104; CHECK-LABEL: v2float_to_v4bf16: 105; CHECK-NEXT: mov v0.16b, v1.16b 106; CHECK-NEXT: ret 107entry: 108 %1 = bitcast <2 x float> %a to <4 x bfloat> 109 ret <4 x bfloat> %1 110} 111 112define <4 x bfloat> @v1double_to_v4bf16(float, <1 x double> %a) nounwind { 113; CHECK-LABEL: v1double_to_v4bf16: 114; CHECK-NEXT: mov v0.16b, v1.16b 115; CHECK-NEXT: ret 116entry: 117 %1 = bitcast <1 x double> %a to <4 x bfloat> 118 ret <4 x bfloat> %1 119} 120 121define <4 x bfloat> @double_to_v4bf16(float, double %a) nounwind { 122; CHECK-LABEL: double_to_v4bf16: 123; CHECK-NEXT: mov v0.16b, v1.16b 124; CHECK-NEXT: ret 125entry: 126 %1 = bitcast double %a to <4 x bfloat> 127 ret <4 x bfloat> %1 128} 129 130define <8 x i16> @v8bf16_to_v8i16(float, <8 x bfloat> %a) nounwind { 131; CHECK-LABEL: v8bf16_to_v8i16: 132; CHECK-NEXT: mov v0.16b, v1.16b 133; CHECK-NEXT: ret 134entry: 135 %1 = bitcast <8 x bfloat> %a to <8 x i16> 136 ret <8 x i16> %1 137} 138 139define <4 x i32> @v8bf16_to_v4i32(float, <8 x bfloat> %a) nounwind { 140; CHECK-LABEL: v8bf16_to_v4i32: 141; CHECK-NEXT: mov v0.16b, v1.16b 142; CHECK-NEXT: ret 143entry: 144 %1 = bitcast <8 x bfloat> %a to <4 x i32> 145 ret <4 x i32> %1 146} 147 148define <2 x i64> @v8bf16_to_v2i64(float, <8 x bfloat> %a) nounwind { 149; CHECK-LABEL: v8bf16_to_v2i64: 150; CHECK-NEXT: mov v0.16b, v1.16b 151; CHECK-NEXT: ret 152entry: 153 %1 = bitcast <8 x bfloat> %a to <2 x i64> 154 ret <2 x i64> %1 155} 156 157define <4 x float> @v8bf16_to_v4float(float, <8 x bfloat> %a) nounwind { 158; CHECK-LABEL: v8bf16_to_v4float: 159; CHECK-NEXT: mov v0.16b, v1.16b 160; CHECK-NEXT: ret 161entry: 162 %1 = bitcast <8 x bfloat> %a to <4 x float> 163 ret <4 x float> %1 164} 165 166define <2 x double> @v8bf16_to_v2double(float, <8 x bfloat> %a) nounwind { 167; CHECK-LABEL: v8bf16_to_v2double: 168; CHECK-NEXT: mov v0.16b, v1.16b 169; CHECK-NEXT: ret 170entry: 171 %1 = bitcast <8 x bfloat> %a to <2 x double> 172 ret <2 x double> %1 173} 174 175define <8 x bfloat> @v8i16_to_v8bf16(float, <8 x i16> %a) nounwind { 176; CHECK-LABEL: v8i16_to_v8bf16: 177; CHECK-NEXT: mov v0.16b, v1.16b 178; CHECK-NEXT: ret 179entry: 180 %1 = bitcast <8 x i16> %a to <8 x bfloat> 181 ret <8 x bfloat> %1 182} 183 184define <8 x bfloat> @v4i32_to_v8bf16(float, <4 x i32> %a) nounwind { 185; CHECK-LABEL: v4i32_to_v8bf16: 186; CHECK-NEXT: mov v0.16b, v1.16b 187; CHECK-NEXT: ret 188entry: 189 %1 = bitcast <4 x i32> %a to <8 x bfloat> 190 ret <8 x bfloat> %1 191} 192 193define <8 x bfloat> @v2i64_to_v8bf16(float, <2 x i64> %a) nounwind { 194; CHECK-LABEL: v2i64_to_v8bf16: 195; CHECK-NEXT: mov v0.16b, v1.16b 196; CHECK-NEXT: ret 197entry: 198 %1 = bitcast <2 x i64> %a to <8 x bfloat> 199 ret <8 x bfloat> %1 200} 201 202define <8 x bfloat> @v4float_to_v8bf16(float, <4 x float> %a) nounwind { 203; CHECK-LABEL: v4float_to_v8bf16: 204; CHECK-NEXT: mov v0.16b, v1.16b 205; CHECK-NEXT: ret 206entry: 207 %1 = bitcast <4 x float> %a to <8 x bfloat> 208 ret <8 x bfloat> %1 209} 210 211define <8 x bfloat> @v2double_to_v8bf16(float, <2 x double> %a) nounwind { 212; CHECK-LABEL: v2double_to_v8bf16: 213; CHECK-NEXT: mov v0.16b, v1.16b 214; CHECK-NEXT: ret 215entry: 216 %1 = bitcast <2 x double> %a to <8 x bfloat> 217 ret <8 x bfloat> %1 218} 219