1; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -O0 -fast-isel=0 -global-isel=false %s -o - | FileCheck -enable-var-scope %s 2; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -O0 -fast-isel=0 -global-isel=false -mattr=+outline-atomics %s -o - | FileCheck -enable-var-scope %s --check-prefix=OUTLINE-ATOMICS 3 4define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind { 5; OUTLINE-ATOMICS: bl __aarch64_cas1_acq_rel 6; CHECK-LABEL: test_cmpxchg_8: 7; CHECK: mov [[ADDR:x[0-9]+]], x0 8; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: 9; CHECK: ldaxrb [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}} 10; CHECK: cmp [[OLD]], w1, uxtb 11; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] 12; CHECK: stlxrb [[STATUS:w[0-9]+]], w2, {{\[}}[[ADDR]]{{\]}} 13; CHECK: cbnz [[STATUS]], [[RETRY]] 14; CHECK: [[DONE]]: 15; CHECK: subs {{w[0-9]+}}, [[OLD]], w1, uxtb 16; CHECK: cset {{w[0-9]+}}, eq 17 %res = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst monotonic 18 ret { i8, i1 } %res 19} 20 21define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind { 22; OUTLINE-ATOMICS: bl __aarch64_cas2_acq_rel 23; CHECK-LABEL: test_cmpxchg_16: 24; CHECK: mov [[ADDR:x[0-9]+]], x0 25; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: 26; CHECK: ldaxrh [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}} 27; CHECK: cmp [[OLD]], w1, uxth 28; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] 29; CHECK: stlxrh [[STATUS:w[3-9]]], w2, {{\[}}[[ADDR]]{{\]}} 30; CHECK: cbnz [[STATUS]], [[RETRY]] 31; CHECK: [[DONE]]: 32; CHECK: subs {{w[0-9]+}}, [[OLD]], w1 33; CHECK: cset {{w[0-9]+}}, eq 34 %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst monotonic 35 ret { i16, i1 } %res 36} 37 38define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind { 39; OUTLINE-ATOMICS: bl __aarch64_cas4_acq_rel 40; CHECK-LABEL: test_cmpxchg_32: 41; CHECK: mov [[ADDR:x[0-9]+]], x0 42; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: 43; CHECK: ldaxr [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}} 44; CHECK: cmp [[OLD]], w1 45; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] 46; CHECK: stlxr [[STATUS:w[0-9]+]], w2, {{\[}}[[ADDR]]{{\]}} 47; CHECK: cbnz [[STATUS]], [[RETRY]] 48; CHECK: [[DONE]]: 49; CHECK: subs {{w[0-9]+}}, [[OLD]], w1 50; CHECK: cset {{w[0-9]+}}, eq 51 %res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic 52 ret { i32, i1 } %res 53} 54 55define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind { 56; OUTLINE-ATOMICS: bl __aarch64_cas8_acq_rel 57; CHECK-LABEL: test_cmpxchg_64: 58; CHECK: mov [[ADDR:x[0-9]+]], x0 59; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: 60; CHECK: ldaxr [[OLD:x[0-9]+]], {{\[}}[[ADDR]]{{\]}} 61; CHECK: cmp [[OLD]], x1 62; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] 63; CHECK: stlxr [[STATUS:w[0-9]+]], x2, {{\[}}[[ADDR]]{{\]}} 64; CHECK: cbnz [[STATUS]], [[RETRY]] 65; CHECK: [[DONE]]: 66; CHECK: subs {{x[0-9]+}}, [[OLD]], x1 67; CHECK: cset {{w[0-9]+}}, eq 68 %res = cmpxchg i64* %addr, i64 %desired, i64 %new seq_cst monotonic 69 ret { i64, i1 } %res 70} 71 72define { i128, i1 } @test_cmpxchg_128(i128* %addr, i128 %desired, i128 %new) nounwind { 73; OUTLINE-ATOMICS: bl __aarch64_cas16_acq_rel 74; CHECK-LABEL: test_cmpxchg_128: 75; CHECK: mov [[ADDR:x[0-9]+]], x0 76; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: 77; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], {{\[}}[[ADDR]]{{\]}} 78; CHECK: cmp [[OLD_LO]], x2 79; CHECK: cset [[CMP_TMP:w[0-9]+]], ne 80; CHECK: cmp [[OLD_HI]], x3 81; CHECK: cinc [[CMP:w[0-9]+]], [[CMP_TMP]], ne 82; CHECK: cbnz [[CMP]], [[DONE:.LBB[0-9]+_[0-9]+]] 83; CHECK: stlxp [[STATUS:w[0-9]+]], x4, x5, {{\[}}[[ADDR]]{{\]}} 84; CHECK: cbnz [[STATUS]], [[RETRY]] 85; CHECK: [[DONE]]: 86 %res = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst monotonic 87 ret { i128, i1 } %res 88} 89 90; Original implementation assumed the desired & new arguments had already been 91; type-legalized into some kind of BUILD_PAIR operation and crashed when this 92; was false. 93@var128 = global i128 0 94define {i128, i1} @test_cmpxchg_128_unsplit(i128* %addr) { 95; OUTLINE-ATOMICS: bl __aarch64_cas16_acq_rel 96; CHECK-LABEL: test_cmpxchg_128_unsplit: 97; CHECK: mov [[ADDR:x[0-9]+]], x0 98; CHECK: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128 99; CHECK: ldp [[DESIRED_LO:x[0-9]+]], [[DESIRED_HI:x[0-9]+]], [x[[VAR128]]] 100; CHECK: ldp [[NEW_LO:x[0-9]+]], [[NEW_HI:x[0-9]+]], [x[[VAR128]]] 101; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: 102; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], {{\[}}[[ADDR]]{{\]}} 103; CHECK: cmp [[OLD_LO]], [[DESIRED_LO]] 104; CHECK: cset [[CMP_TMP:w[0-9]+]], ne 105; CHECK: cmp [[OLD_HI]], [[DESIRED_HI]] 106; CHECK: cinc [[CMP:w[0-9]+]], [[CMP_TMP]], ne 107; CHECK: cbnz [[CMP]], [[DONE:.LBB[0-9]+_[0-9]+]] 108; CHECK: stlxp [[STATUS:w[0-9]+]], [[NEW_LO]], [[NEW_HI]], {{\[}}[[ADDR]]{{\]}} 109; CHECK: cbnz [[STATUS]], [[RETRY]] 110; CHECK: [[DONE]]: 111 112 %desired = load volatile i128, i128* @var128 113 %new = load volatile i128, i128* @var128 114 %val = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst 115 ret { i128, i1 } %val 116} 117