1# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=early-ifcvt -verify-machineinstrs %s -o - | FileCheck %s 2--- | 3 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 4 target triple = "arm64-apple-ios13.3.0" 5 define hidden void @phi_operands_regclasses_different() #0 { 6 entry: 7 br i1 undef, label %if.then139.i, label %if.else142.i 8 9 if.then139.i: ; preds = %entry 10 %0 = load double, double* undef, align 8 11 br label %if.end161.i 12 13 if.else142.i: ; preds = %entry 14 %tobool154.i = icmp eq i8 undef, 0 15 br i1 %tobool154.i, label %if.then155.i, label %if.end161.i 16 17 if.then155.i: ; preds = %if.else142.i 18 %add158.i = fadd double undef, 0.000000e+00 19 br label %if.end161.i 20 21 if.end161.i: ; preds = %if.then155.i, %if.else142.i, %if.then139.i 22 %y2.0.i = phi double [ %0, %if.then139.i ], [ 0.000000e+00, %if.else142.i ], [ 0.000000e+00, %if.then155.i ] 23 %add169.i = fadd double 0.000000e+00, %y2.0.i 24 %1 = fmul double undef, %add169.i 25 %add174.i = fsub double undef, %1 26 %2 = call double @llvm.fabs.f64(double %add174.i) #2 27 %cmp.i516.i = fcmp olt double %2, 0x3BC79CA10C924223 28 br i1 %cmp.i516.i, label %if.then.i.i, label %if.end9.i.i 29 30 if.then.i.i: ; preds = %if.end161.i 31 %3 = call double @llvm.fabs.f64(double undef) #2 32 unreachable 33 34 if.end9.i.i: ; preds = %if.end161.i 35 ret void 36 } 37 declare double @llvm.fabs.f64(double) #1 38 declare void @llvm.stackprotector(i8*, i8**) #2 39 40 attributes #0 = { "target-cpu"="apple-a7" } 41 attributes #1 = { nounwind readnone speculatable willreturn } 42 attributes #2 = { nounwind } 43 44 !llvm.ident = !{!0} 45 46 !0 = !{!"clang"} 47 48... 49--- 50name: phi_operands_regclasses_different 51alignment: 4 52exposesReturnsTwice: false 53legalized: true 54regBankSelected: true 55selected: true 56failedISel: false 57tracksRegLiveness: true 58hasWinCFI: false 59registers: 60 - { id: 0, class: gpr32, preferred-register: '' } 61 - { id: 1, class: _, preferred-register: '' } 62 - { id: 2, class: _, preferred-register: '' } 63 - { id: 3, class: gpr, preferred-register: '' } 64 - { id: 4, class: gpr64, preferred-register: '' } 65 - { id: 5, class: fpr, preferred-register: '' } 66 - { id: 6, class: _, preferred-register: '' } 67 - { id: 7, class: gpr64, preferred-register: '' } 68 - { id: 8, class: gpr64common, preferred-register: '' } 69 - { id: 9, class: gpr64, preferred-register: '' } 70 - { id: 10, class: fpr64, preferred-register: '' } 71 - { id: 11, class: fpr64, preferred-register: '' } 72 - { id: 12, class: fpr, preferred-register: '' } 73 - { id: 13, class: fpr64, preferred-register: '' } 74 - { id: 14, class: fpr, preferred-register: '' } 75 - { id: 15, class: gpr32, preferred-register: '' } 76 - { id: 16, class: _, preferred-register: '' } 77 - { id: 17, class: gpr32, preferred-register: '' } 78 - { id: 18, class: gpr32, preferred-register: '' } 79 - { id: 19, class: gpr32, preferred-register: '' } 80 - { id: 20, class: gpr, preferred-register: '' } 81 - { id: 21, class: fpr64, preferred-register: '' } 82 - { id: 22, class: fpr64, preferred-register: '' } 83 - { id: 23, class: fpr64, preferred-register: '' } 84 - { id: 24, class: fpr64, preferred-register: '' } 85 - { id: 25, class: fpr64, preferred-register: '' } 86 - { id: 26, class: fpr64, preferred-register: '' } 87 - { id: 27, class: fpr64, preferred-register: '' } 88 - { id: 28, class: gpr64, preferred-register: '' } 89liveins: [] 90frameInfo: 91 isFrameAddressTaken: false 92 isReturnAddressTaken: false 93 hasStackMap: false 94 hasPatchPoint: false 95 stackSize: 0 96 offsetAdjustment: 0 97 maxAlignment: 1 98 adjustsStack: false 99 hasCalls: false 100 stackProtector: '' 101 maxCallFrameSize: 0 102 cvBytesOfCalleeSavedRegisters: 0 103 hasOpaqueSPAdjustment: false 104 hasVAStart: false 105 hasMustTailInVarArgFunc: false 106 localFrameSize: 0 107 savePoint: '' 108 restorePoint: '' 109fixedStack: [] 110stack: [] 111callSites: [] 112constants: [] 113machineFunctionInfo: {} 114body: | 115 ; Here we check that we don't ifcvt to a CSEL that uses GPRs, because 116 ; some operands to the PHI have the fpr64 regclass. 117 ; CHECK-LABEL: name: phi_operands_regclasses_different 118 ; CHECK-NOT: CSELXr 119 bb.1.entry: 120 successors: %bb.2(0x40000000), %bb.3(0x40000000) 121 122 %0:gpr32 = IMPLICIT_DEF 123 %4:gpr64 = IMPLICIT_DEF 124 %8:gpr64common = IMPLICIT_DEF 125 TBNZW %0, 0, %bb.2 126 B %bb.3 127 128 bb.2.if.then139.i: 129 successors: %bb.5(0x80000000) 130 131 %7:gpr64 = LDRXui %8, 0 :: (load 8 from `double* undef`) 132 B %bb.5 133 134 bb.3.if.else142.i: 135 successors: %bb.4(0x40000000), %bb.5(0x40000000) 136 137 %26:fpr64 = FMOVD0 138 %19:gpr32 = COPY $wzr 139 CBNZW %19, %bb.5 140 141 bb.4.if.then155.i: 142 successors: %bb.5(0x80000000) 143 144 %27:fpr64 = FMOVD0 145 146 bb.5.if.end161.i: 147 successors: %bb.6(0x40000000), %bb.7(0x40000000) 148 149 %9:gpr64 = PHI %7, %bb.2, %26, %bb.3, %27, %bb.4 150 %21:fpr64 = COPY %9 151 %25:fpr64 = FMOVD0 152 %10:fpr64 = FADDDrr %25, %21 153 %22:fpr64 = COPY %4 154 %11:fpr64 = FMULDrr %22, %10 155 %23:fpr64 = COPY %4 156 %13:fpr64 = FABD64 %23, %11 157 %28:gpr64 = MOVi64imm 4307583784117748259 158 %24:fpr64 = COPY %28 159 FCMPDrr %13, %24, implicit-def $nzcv 160 %17:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv 161 TBNZW %17, 0, %bb.6 162 B %bb.7 163 164 bb.6.if.then.i.i: 165 successors: 166 167 168 bb.7.if.end9.i.i: 169 RET_ReallyLR 170 171... 172