1; RUN: llc -fast-isel -fast-isel-abort=1 -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s 2 3; CHECK-LABEL: asr_zext_i1_i16 4; CHECK: uxth {{w[0-9]*}}, wzr 5define zeroext i16 @asr_zext_i1_i16(i1 %b) { 6 %1 = zext i1 %b to i16 7 %2 = ashr i16 %1, 1 8 ret i16 %2 9} 10 11; CHECK-LABEL: asr_sext_i1_i16 12; CHECK: sbfx [[REG1:w[0-9]+]], {{w[0-9]*}}, #0, #1 13; CHECK-NEXT: sxth {{w[0-9]*}}, [[REG1]] 14define signext i16 @asr_sext_i1_i16(i1 %b) { 15 %1 = sext i1 %b to i16 16 %2 = ashr i16 %1, 1 17 ret i16 %2 18} 19 20; CHECK-LABEL: asr_zext_i1_i32 21; CHECK: mov {{w[0-9]*}}, wzr 22define i32 @asr_zext_i1_i32(i1 %b) { 23 %1 = zext i1 %b to i32 24 %2 = ashr i32 %1, 1 25 ret i32 %2 26} 27 28; CHECK-LABEL: asr_sext_i1_i32 29; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #0, #1 30define i32 @asr_sext_i1_i32(i1 %b) { 31 %1 = sext i1 %b to i32 32 %2 = ashr i32 %1, 1 33 ret i32 %2 34} 35 36; CHECK-LABEL: asr_zext_i1_i64 37; CHECK: mov {{x[0-9]*}}, xzr 38define i64 @asr_zext_i1_i64(i1 %b) { 39 %1 = zext i1 %b to i64 40 %2 = ashr i64 %1, 1 41 ret i64 %2 42} 43 44; CHECK-LABEL: asr_sext_i1_i64 45; CHECK: sbfx {{x[0-9]*}}, {{x[0-9]*}}, #0, #1 46define i64 @asr_sext_i1_i64(i1 %b) { 47 %1 = sext i1 %b to i64 48 %2 = ashr i64 %1, 1 49 ret i64 %2 50} 51 52; CHECK-LABEL: lsr_zext_i1_i16 53; CHECK: uxth {{w[0-9]*}}, wzr 54define zeroext i16 @lsr_zext_i1_i16(i1 %b) { 55 %1 = zext i1 %b to i16 56 %2 = lshr i16 %1, 1 57 ret i16 %2 58} 59 60; CHECK-LABEL: lsr_sext_i1_i16 61; CHECK: sbfx [[REG1:w[0-9]+]], {{w[0-9]*}}, #0, #1 62; CHECK-NEXT: ubfx [[REG2:w[0-9]+]], [[REG1]], #1, #15 63; CHECK-NEXT: sxth {{w[0-9]*}}, [[REG2]] 64define signext i16 @lsr_sext_i1_i16(i1 %b) { 65 %1 = sext i1 %b to i16 66 %2 = lshr i16 %1, 1 67 ret i16 %2 68} 69 70; CHECK-LABEL: lsr_zext_i1_i32 71; CHECK: mov {{w[0-9]*}}, wzr 72define i32 @lsr_zext_i1_i32(i1 %b) { 73 %1 = zext i1 %b to i32 74 %2 = lshr i32 %1, 1 75 ret i32 %2 76} 77 78; CHECK-LABEL: lsr_sext_i1_i32 79; CHECK: sbfx [[REG1:w[0-9]+]], {{w[0-9]*}}, #0, #1 80; CHECK-NEXT: lsr {{w[0-9]*}}, [[REG1:w[0-9]+]], #1 81define i32 @lsr_sext_i1_i32(i1 %b) { 82 %1 = sext i1 %b to i32 83 %2 = lshr i32 %1, 1 84 ret i32 %2 85} 86 87; CHECK-LABEL: lsr_zext_i1_i64 88; CHECK: mov {{x[0-9]*}}, xzr 89define i64 @lsr_zext_i1_i64(i1 %b) { 90 %1 = zext i1 %b to i64 91 %2 = lshr i64 %1, 1 92 ret i64 %2 93} 94 95; CHECK-LABEL: lsl_zext_i1_i16 96; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1 97define zeroext i16 @lsl_zext_i1_i16(i1 %b) { 98 %1 = zext i1 %b to i16 99 %2 = shl i16 %1, 4 100 ret i16 %2 101} 102 103; CHECK-LABEL: lsl_sext_i1_i16 104; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1 105define signext i16 @lsl_sext_i1_i16(i1 %b) { 106 %1 = sext i1 %b to i16 107 %2 = shl i16 %1, 4 108 ret i16 %2 109} 110 111; CHECK-LABEL: lsl_zext_i1_i32 112; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1 113define i32 @lsl_zext_i1_i32(i1 %b) { 114 %1 = zext i1 %b to i32 115 %2 = shl i32 %1, 4 116 ret i32 %2 117} 118 119; CHECK-LABEL: lsl_sext_i1_i32 120; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1 121define i32 @lsl_sext_i1_i32(i1 %b) { 122 %1 = sext i1 %b to i32 123 %2 = shl i32 %1, 4 124 ret i32 %2 125} 126 127; CHECK-LABEL: lsl_zext_i1_i64 128; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1 129define i64 @lsl_zext_i1_i64(i1 %b) { 130 %1 = zext i1 %b to i64 131 %2 = shl i64 %1, 4 132 ret i64 %2 133} 134 135; CHECK-LABEL: lsl_sext_i1_i64 136; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1 137define i64 @lsl_sext_i1_i64(i1 %b) { 138 %1 = sext i1 %b to i64 139 %2 = shl i64 %1, 4 140 ret i64 %2 141} 142 143; CHECK-LABEL: lslv_i8 144; CHECK: and [[REG1:w[0-9]+]], w1, #0xff 145; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]] 146; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xff 147define zeroext i8 @lslv_i8(i8 %a, i8 %b) { 148 %1 = shl i8 %a, %b 149 ret i8 %1 150} 151 152; CHECK-LABEL: lsl_i8 153; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4 154define zeroext i8 @lsl_i8(i8 %a) { 155 %1 = shl i8 %a, 4 156 ret i8 %1 157} 158 159; CHECK-LABEL: lsl_zext_i8_i16 160; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8 161define zeroext i16 @lsl_zext_i8_i16(i8 %b) { 162 %1 = zext i8 %b to i16 163 %2 = shl i16 %1, 4 164 ret i16 %2 165} 166 167; CHECK-LABEL: lsl_sext_i8_i16 168; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8 169define signext i16 @lsl_sext_i8_i16(i8 %b) { 170 %1 = sext i8 %b to i16 171 %2 = shl i16 %1, 4 172 ret i16 %2 173} 174 175; CHECK-LABEL: lsl_zext_i8_i32 176; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8 177define i32 @lsl_zext_i8_i32(i8 %b) { 178 %1 = zext i8 %b to i32 179 %2 = shl i32 %1, 4 180 ret i32 %2 181} 182 183; CHECK-LABEL: lsl_sext_i8_i32 184; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8 185define i32 @lsl_sext_i8_i32(i8 %b) { 186 %1 = sext i8 %b to i32 187 %2 = shl i32 %1, 4 188 ret i32 %2 189} 190 191; CHECK-LABEL: lsl_zext_i8_i64 192; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8 193define i64 @lsl_zext_i8_i64(i8 %b) { 194 %1 = zext i8 %b to i64 195 %2 = shl i64 %1, 4 196 ret i64 %2 197} 198 199; CHECK-LABEL: lsl_sext_i8_i64 200; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8 201define i64 @lsl_sext_i8_i64(i8 %b) { 202 %1 = sext i8 %b to i64 203 %2 = shl i64 %1, 4 204 ret i64 %2 205} 206 207; CHECK-LABEL: lslv_i16 208; CHECK: and [[REG1:w[0-9]+]], w1, #0xffff 209; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]] 210; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xffff 211define zeroext i16 @lslv_i16(i16 %a, i16 %b) { 212 %1 = shl i16 %a, %b 213 ret i16 %1 214} 215 216; CHECK-LABEL: lsl_i16 217; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #8 218define zeroext i16 @lsl_i16(i16 %a) { 219 %1 = shl i16 %a, 8 220 ret i16 %1 221} 222 223; CHECK-LABEL: lsl_zext_i16_i32 224; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16 225define i32 @lsl_zext_i16_i32(i16 %b) { 226 %1 = zext i16 %b to i32 227 %2 = shl i32 %1, 8 228 ret i32 %2 229} 230 231; CHECK-LABEL: lsl_sext_i16_i32 232; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16 233define i32 @lsl_sext_i16_i32(i16 %b) { 234 %1 = sext i16 %b to i32 235 %2 = shl i32 %1, 8 236 ret i32 %2 237} 238 239; CHECK-LABEL: lsl_zext_i16_i64 240; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16 241define i64 @lsl_zext_i16_i64(i16 %b) { 242 %1 = zext i16 %b to i64 243 %2 = shl i64 %1, 8 244 ret i64 %2 245} 246 247; CHECK-LABEL: lsl_sext_i16_i64 248; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16 249define i64 @lsl_sext_i16_i64(i16 %b) { 250 %1 = sext i16 %b to i64 251 %2 = shl i64 %1, 8 252 ret i64 %2 253} 254 255; CHECK-LABEL: lslv_i32 256; CHECK: lsl {{w[0-9]*}}, w0, w1 257define zeroext i32 @lslv_i32(i32 %a, i32 %b) { 258 %1 = shl i32 %a, %b 259 ret i32 %1 260} 261 262; CHECK-LABEL: lsl_i32 263; CHECK: lsl {{w[0-9]*}}, {{w[0-9]*}}, #16 264define zeroext i32 @lsl_i32(i32 %a) { 265 %1 = shl i32 %a, 16 266 ret i32 %1 267} 268 269; CHECK-LABEL: lsl_zext_i32_i64 270; CHECK: ubfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32 271define i64 @lsl_zext_i32_i64(i32 %b) { 272 %1 = zext i32 %b to i64 273 %2 = shl i64 %1, 16 274 ret i64 %2 275} 276 277; CHECK-LABEL: lsl_sext_i32_i64 278; CHECK: sbfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32 279define i64 @lsl_sext_i32_i64(i32 %b) { 280 %1 = sext i32 %b to i64 281 %2 = shl i64 %1, 16 282 ret i64 %2 283} 284 285; CHECK-LABEL: lslv_i64 286; CHECK: lsl {{x[0-9]*}}, x0, x1 287define i64 @lslv_i64(i64 %a, i64 %b) { 288 %1 = shl i64 %a, %b 289 ret i64 %1 290} 291 292; CHECK-LABEL: lsl_i64 293; CHECK: lsl {{x[0-9]*}}, {{x[0-9]*}}, #32 294define i64 @lsl_i64(i64 %a) { 295 %1 = shl i64 %a, 32 296 ret i64 %1 297} 298 299; CHECK-LABEL: lsrv_i8 300; CHECK: and [[REG1:w[0-9]+]], w0, #0xff 301; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff 302; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]] 303; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff 304define zeroext i8 @lsrv_i8(i8 %a, i8 %b) { 305 %1 = lshr i8 %a, %b 306 ret i8 %1 307} 308 309; CHECK-LABEL: lsr_i8 310; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4 311define zeroext i8 @lsr_i8(i8 %a) { 312 %1 = lshr i8 %a, 4 313 ret i8 %1 314} 315 316; CHECK-LABEL: lsr_zext_i8_i16 317; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4 318define zeroext i16 @lsr_zext_i8_i16(i8 %b) { 319 %1 = zext i8 %b to i16 320 %2 = lshr i16 %1, 4 321 ret i16 %2 322} 323 324; CHECK-LABEL: lsr_sext_i8_i16 325; CHECK: sxtb [[REG:w[0-9]+]], w0 326; CHECK-NEXT: ubfx {{w[0-9]*}}, [[REG]], #4, #12 327define signext i16 @lsr_sext_i8_i16(i8 %b) { 328 %1 = sext i8 %b to i16 329 %2 = lshr i16 %1, 4 330 ret i16 %2 331} 332 333; CHECK-LABEL: lsr_zext_i8_i32 334; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4 335define i32 @lsr_zext_i8_i32(i8 %b) { 336 %1 = zext i8 %b to i32 337 %2 = lshr i32 %1, 4 338 ret i32 %2 339} 340 341; CHECK-LABEL: lsr_sext_i8_i32 342; CHECK: sxtb [[REG:w[0-9]+]], w0 343; CHECK-NEXT: lsr {{w[0-9]*}}, [[REG]], #4 344define i32 @lsr_sext_i8_i32(i8 %b) { 345 %1 = sext i8 %b to i32 346 %2 = lshr i32 %1, 4 347 ret i32 %2 348} 349 350; CHECK-LABEL: lsrv_i16 351; CHECK: and [[REG1:w[0-9]+]], w0, #0xffff 352; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff 353; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]] 354; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff 355define zeroext i16 @lsrv_i16(i16 %a, i16 %b) { 356 %1 = lshr i16 %a, %b 357 ret i16 %1 358} 359 360; CHECK-LABEL: lsr_i16 361; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8 362define zeroext i16 @lsr_i16(i16 %a) { 363 %1 = lshr i16 %a, 8 364 ret i16 %1 365} 366 367; CHECK-LABEL: lsrv_i32 368; CHECK: lsr {{w[0-9]*}}, w0, w1 369define zeroext i32 @lsrv_i32(i32 %a, i32 %b) { 370 %1 = lshr i32 %a, %b 371 ret i32 %1 372} 373 374; CHECK-LABEL: lsr_i32 375; CHECK: lsr {{w[0-9]*}}, {{w[0-9]*}}, #16 376define zeroext i32 @lsr_i32(i32 %a) { 377 %1 = lshr i32 %a, 16 378 ret i32 %1 379} 380 381; CHECK-LABEL: lsrv_i64 382; CHECK: lsr {{x[0-9]*}}, x0, x1 383define i64 @lsrv_i64(i64 %a, i64 %b) { 384 %1 = lshr i64 %a, %b 385 ret i64 %1 386} 387 388; CHECK-LABEL: lsr_i64 389; CHECK: lsr {{x[0-9]*}}, {{x[0-9]*}}, #32 390define i64 @lsr_i64(i64 %a) { 391 %1 = lshr i64 %a, 32 392 ret i64 %1 393} 394 395; CHECK-LABEL: asrv_i8 396; CHECK: sxtb [[REG1:w[0-9]+]], w0 397; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff 398; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]] 399; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff 400define zeroext i8 @asrv_i8(i8 %a, i8 %b) { 401 %1 = ashr i8 %a, %b 402 ret i8 %1 403} 404 405; CHECK-LABEL: asr_i8 406; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4 407define zeroext i8 @asr_i8(i8 %a) { 408 %1 = ashr i8 %a, 4 409 ret i8 %1 410} 411 412; CHECK-LABEL: asr_zext_i8_i16 413; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4 414define zeroext i16 @asr_zext_i8_i16(i8 %b) { 415 %1 = zext i8 %b to i16 416 %2 = ashr i16 %1, 4 417 ret i16 %2 418} 419 420; CHECK-LABEL: asr_sext_i8_i16 421; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4 422define signext i16 @asr_sext_i8_i16(i8 %b) { 423 %1 = sext i8 %b to i16 424 %2 = ashr i16 %1, 4 425 ret i16 %2 426} 427 428; CHECK-LABEL: asr_zext_i8_i32 429; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4 430define i32 @asr_zext_i8_i32(i8 %b) { 431 %1 = zext i8 %b to i32 432 %2 = ashr i32 %1, 4 433 ret i32 %2 434} 435 436; CHECK-LABEL: asr_sext_i8_i32 437; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4 438define i32 @asr_sext_i8_i32(i8 %b) { 439 %1 = sext i8 %b to i32 440 %2 = ashr i32 %1, 4 441 ret i32 %2 442} 443 444; CHECK-LABEL: asrv_i16 445; CHECK: sxth [[REG1:w[0-9]+]], w0 446; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff 447; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]] 448; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff 449define zeroext i16 @asrv_i16(i16 %a, i16 %b) { 450 %1 = ashr i16 %a, %b 451 ret i16 %1 452} 453 454; CHECK-LABEL: asr_i16 455; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8 456define zeroext i16 @asr_i16(i16 %a) { 457 %1 = ashr i16 %a, 8 458 ret i16 %1 459} 460 461; CHECK-LABEL: asrv_i32 462; CHECK: asr {{w[0-9]*}}, w0, w1 463define zeroext i32 @asrv_i32(i32 %a, i32 %b) { 464 %1 = ashr i32 %a, %b 465 ret i32 %1 466} 467 468; CHECK-LABEL: asr_i32 469; CHECK: asr {{w[0-9]*}}, {{w[0-9]*}}, #16 470define zeroext i32 @asr_i32(i32 %a) { 471 %1 = ashr i32 %a, 16 472 ret i32 %1 473} 474 475; CHECK-LABEL: asrv_i64 476; CHECK: asr {{x[0-9]*}}, x0, x1 477define i64 @asrv_i64(i64 %a, i64 %b) { 478 %1 = ashr i64 %a, %b 479 ret i64 %1 480} 481 482; CHECK-LABEL: asr_i64 483; CHECK: asr {{x[0-9]*}}, {{x[0-9]*}}, #32 484define i64 @asr_i64(i64 %a) { 485 %1 = ashr i64 %a, 32 486 ret i64 %1 487} 488 489; CHECK-LABEL: shift_test1 490; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4 491; CHECK-NEXT: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4 492define i32 @shift_test1(i8 %a) { 493 %1 = shl i8 %a, 4 494 %2 = ashr i8 %1, 4 495 %3 = sext i8 %2 to i32 496 ret i32 %3 497} 498 499; Test zero shifts 500 501; CHECK-LABEL: shl_zero 502; CHECK-NOT: lsl 503define i32 @shl_zero(i32 %a) { 504 %1 = shl i32 %a, 0 505 ret i32 %1 506} 507 508; CHECK-LABEL: lshr_zero 509; CHECK-NOT: lsr 510define i32 @lshr_zero(i32 %a) { 511 %1 = lshr i32 %a, 0 512 ret i32 %1 513} 514 515; CHECK-LABEL: ashr_zero 516; CHECK-NOT: asr 517define i32 @ashr_zero(i32 %a) { 518 %1 = ashr i32 %a, 0 519 ret i32 %1 520} 521 522; CHECK-LABEL: shl_zext_zero 523; CHECK: ubfx x0, x0, #0, #32 524define i64 @shl_zext_zero(i32 %a) { 525 %1 = zext i32 %a to i64 526 %2 = shl i64 %1, 0 527 ret i64 %2 528} 529 530; CHECK-LABEL: lshr_zext_zero 531; CHECK: ubfx x0, x0, #0, #32 532define i64 @lshr_zext_zero(i32 %a) { 533 %1 = zext i32 %a to i64 534 %2 = lshr i64 %1, 0 535 ret i64 %2 536} 537 538; CHECK-LABEL: ashr_zext_zero 539; CHECK: ubfx x0, x0, #0, #32 540define i64 @ashr_zext_zero(i32 %a) { 541 %1 = zext i32 %a to i64 542 %2 = ashr i64 %1, 0 543 ret i64 %2 544} 545 546