1; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s 2 3; CHECK-LABEL: testmsws: 4; CHECK: frintx [[REG:s[0-9]]], s0 5; CHECK-NEXT: fcvtzs x0, [[REG]] 6; CHECK: ret 7define i32 @testmsws(float %x) { 8entry: 9 %0 = tail call i64 @llvm.llrint.f32(float %x) 10 %conv = trunc i64 %0 to i32 11 ret i32 %conv 12} 13 14; CHECK-LABEL: testmsxs: 15; CHECK: frintx [[REG:s[0-9]]], s0 16; CHECK-NEXT: fcvtzs x0, [[REG]] 17; CHECK-NEXT: ret 18define i64 @testmsxs(float %x) { 19entry: 20 %0 = tail call i64 @llvm.llrint.f32(float %x) 21 ret i64 %0 22} 23 24; CHECK-LABEL: testmswd: 25; CHECK: frintx [[REG:d[0-9]]], d0 26; CHECK-NEXT: fcvtzs x0, [[REG]] 27; CHECK: ret 28define i32 @testmswd(double %x) { 29entry: 30 %0 = tail call i64 @llvm.llrint.f64(double %x) 31 %conv = trunc i64 %0 to i32 32 ret i32 %conv 33} 34 35; CHECK-LABEL: testmsxd: 36; CHECK: frintx [[REG:d[0-9]]], d0 37; CHECK-NEXT: fcvtzs x0, [[REG]] 38; CHECK-nEXT: ret 39define i64 @testmsxd(double %x) { 40entry: 41 %0 = tail call i64 @llvm.llrint.f64(double %x) 42 ret i64 %0 43} 44 45; CHECK-LABEL: testmswl: 46; CHECK: bl llrintl 47define i32 @testmswl(fp128 %x) { 48entry: 49 %0 = tail call i64 @llvm.llrint.f128(fp128 %x) 50 %conv = trunc i64 %0 to i32 51 ret i32 %conv 52} 53 54; CHECK-LABEL: testmsll: 55; CHECK: b llrintl 56define i64 @testmsll(fp128 %x) { 57entry: 58 %0 = tail call i64 @llvm.llrint.f128(fp128 %x) 59 ret i64 %0 60} 61 62declare i64 @llvm.llrint.f32(float) nounwind readnone 63declare i64 @llvm.llrint.f64(double) nounwind readnone 64declare i64 @llvm.llrint.f128(fp128) nounwind readnone 65