1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone -mattr=+slow-misaligned-128store | FileCheck %s --check-prefixes=CHECK,SPLITTING 3; RUN: llc < %s -mtriple=aarch64-eabi -mattr=-slow-misaligned-128store | FileCheck %s --check-prefixes=CHECK,MISALIGNED 4 5@g0 = external dso_local global <3 x float>, align 16 6@g1 = external dso_local global <3 x float>, align 4 7 8define void @blam() { 9; SPLITTING-LABEL: blam: 10; SPLITTING: // %bb.0: 11; SPLITTING-NEXT: adrp x8, g1 12; SPLITTING-NEXT: add x8, x8, :lo12:g1 13; SPLITTING-NEXT: adrp x9, g0 14; SPLITTING-NEXT: ldr q0, [x9, :lo12:g0] 15; SPLITTING-NEXT: str d0, [x8] 16; SPLITTING-NEXT: ret 17; 18; MISALIGNED-LABEL: blam: 19; MISALIGNED: // %bb.0: 20; MISALIGNED-NEXT: adrp x8, g0 21; MISALIGNED-NEXT: ldr q0, [x8, :lo12:g0] 22; MISALIGNED-NEXT: adrp x8, g1 23; MISALIGNED-NEXT: add x8, x8, :lo12:g1 24; MISALIGNED-NEXT: str d0, [x8] 25; MISALIGNED-NEXT: ret 26 %tmp4 = getelementptr inbounds <3 x float>, <3 x float>* @g1, i64 0, i64 0 27 %tmp5 = load <3 x float>, <3 x float>* @g0, align 16 28 %tmp6 = extractelement <3 x float> %tmp5, i64 0 29 store float %tmp6, float* %tmp4 30 %tmp7 = getelementptr inbounds float, float* %tmp4, i64 1 31 %tmp8 = load <3 x float>, <3 x float>* @g0, align 16 32 %tmp9 = extractelement <3 x float> %tmp8, i64 1 33 store float %tmp9, float* %tmp7 34 ret void; 35} 36 37 38; PR21711 - Merge vector stores into wider vector stores. 39 40; On Cyclone, the stores should not get merged into a 16-byte store because 41; unaligned 16-byte stores are slow. This test would infinite loop when 42; the fastness of unaligned accesses was not specified correctly. 43 44define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) { 45; CHECK-LABEL: merge_vec_extract_stores: 46; CHECK: // %bb.0: 47; CHECK-NEXT: stur q0, [x0, #24] 48; CHECK-NEXT: ret 49 %idx0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3 50 %idx1 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 4 51 52 %shuffle0 = shufflevector <4 x float> %v1, <4 x float> undef, <2 x i32> <i32 0, i32 1> 53 %shuffle1 = shufflevector <4 x float> %v1, <4 x float> undef, <2 x i32> <i32 2, i32 3> 54 55 store <2 x float> %shuffle0, <2 x float>* %idx0, align 8 56 store <2 x float> %shuffle1, <2 x float>* %idx1, align 8 57 ret void 58} 59