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1; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=instruction-select < %s | FileCheck %s
2
3declare void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float>, <4 x float>, float*)
4declare void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
5declare void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)
6
7declare void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float>, <4 x float>, float*)
8declare void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
9declare void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)
10
11declare void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float>, <4 x float>, i64, float*)
12declare void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, i64, float*)
13declare void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, i64, float*)
14
15define void @addstx(float* %res, <4 x float>* %a,  <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
16  %al = load <4 x float>, <4 x float>* %a
17  %bl = load <4 x float>, <4 x float>* %b
18  %cl = load <4 x float>, <4 x float>* %c
19  %dl = load <4 x float>, <4 x float>* %d
20
21  %ar = fadd <4 x float> %al, %bl
22  %br = fadd <4 x float> %bl, %cl
23  %cr = fadd <4 x float> %cl, %dl
24  %dr = fadd <4 x float> %dl, %al
25
26; The sizes below are conservative.  AArch64TargetLowering
27; conservatively assumes the entire vector is stored.
28  tail call void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)
29; CHECK: ST2Twov4s {{.*}} :: (store 32 {{.*}})
30  tail call void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)
31; CHECK: ST3Threev4s {{.*}} :: (store 48 {{.*}})
32  tail call void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)
33; CHECK: ST4Fourv4s {{.*}} :: (store 64 {{.*}})
34
35  ret void
36}
37
38define void @addst1x(float* %res, <4 x float>* %a,  <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
39  %al = load <4 x float>, <4 x float>* %a
40  %bl = load <4 x float>, <4 x float>* %b
41  %cl = load <4 x float>, <4 x float>* %c
42  %dl = load <4 x float>, <4 x float>* %d
43
44  %ar = fadd <4 x float> %al, %bl
45  %br = fadd <4 x float> %bl, %cl
46  %cr = fadd <4 x float> %cl, %dl
47  %dr = fadd <4 x float> %dl, %al
48
49; The sizes below are conservative.  AArch64TargetLowering
50; conservatively assumes the entire vector is stored.
51  tail call void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)
52; CHECK: ST1Twov4s {{.*}} :: (store 32 {{.*}})
53  tail call void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)
54; CHECK: ST1Threev4s {{.*}} :: (store 48 {{.*}})
55  tail call void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)
56; CHECK: ST1Fourv4s {{.*}} :: (store 64 {{.*}})
57
58  ret void
59}
60
61define void @addstxlane(float* %res, <4 x float>* %a,  <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
62  %al = load <4 x float>, <4 x float>* %a
63  %bl = load <4 x float>, <4 x float>* %b
64  %cl = load <4 x float>, <4 x float>* %c
65  %dl = load <4 x float>, <4 x float>* %d
66
67  %ar = fadd <4 x float> %al, %bl
68  %br = fadd <4 x float> %bl, %cl
69  %cr = fadd <4 x float> %cl, %dl
70  %dr = fadd <4 x float> %dl, %al
71
72; The sizes below are conservative.  AArch64TargetLowering
73; conservatively assumes the entire vector is stored.
74  tail call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, i64 1, float* %res)
75; CHECK: ST2i32 {{.*}} :: (store 32 {{.*}})
76  tail call void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, i64 1, float* %res)
77; CHECK: ST3i32 {{.*}} :: (store 48 {{.*}})
78  tail call void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, i64 1, float* %res)
79; CHECK: ST4i32 {{.*}} :: (store 64 {{.*}})
80
81  ret void
82}
83