1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s 3 4define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) { 5; CHECK-LABEL: and8xi8: 6; CHECK: // %bb.0: 7; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 8; CHECK-NEXT: ret 9 %tmp1 = and <8 x i8> %a, %b; 10 ret <8 x i8> %tmp1 11} 12 13define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) { 14; CHECK-LABEL: and16xi8: 15; CHECK: // %bb.0: 16; CHECK-NEXT: and v0.16b, v0.16b, v1.16b 17; CHECK-NEXT: ret 18 %tmp1 = and <16 x i8> %a, %b; 19 ret <16 x i8> %tmp1 20} 21 22 23define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) { 24; CHECK-LABEL: orr8xi8: 25; CHECK: // %bb.0: 26; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b 27; CHECK-NEXT: ret 28 %tmp1 = or <8 x i8> %a, %b; 29 ret <8 x i8> %tmp1 30} 31 32define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) { 33; CHECK-LABEL: orr16xi8: 34; CHECK: // %bb.0: 35; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 36; CHECK-NEXT: ret 37 %tmp1 = or <16 x i8> %a, %b; 38 ret <16 x i8> %tmp1 39} 40 41 42define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) { 43; CHECK-LABEL: xor8xi8: 44; CHECK: // %bb.0: 45; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b 46; CHECK-NEXT: ret 47 %tmp1 = xor <8 x i8> %a, %b; 48 ret <8 x i8> %tmp1 49} 50 51define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) { 52; CHECK-LABEL: xor16xi8: 53; CHECK: // %bb.0: 54; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b 55; CHECK-NEXT: ret 56 %tmp1 = xor <16 x i8> %a, %b; 57 ret <16 x i8> %tmp1 58} 59 60define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) { 61; CHECK-LABEL: bsl8xi8_const: 62; CHECK: // %bb.0: 63; CHECK-NEXT: movi d2, #0x00ffff0000ffff 64; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b 65; CHECK-NEXT: ret 66 %tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 > 67 %tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1 > 68 %tmp3 = or <8 x i8> %tmp1, %tmp2 69 ret <8 x i8> %tmp3 70} 71 72define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) { 73; CHECK-LABEL: bsl16xi8_const: 74; CHECK: // %bb.0: 75; CHECK-NEXT: movi v2.2d, #0x000000ffffffff 76; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b 77; CHECK-NEXT: ret 78 %tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0 > 79 %tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1 > 80 %tmp3 = or <16 x i8> %tmp1, %tmp2 81 ret <16 x i8> %tmp3 82} 83 84define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) { 85; CHECK-LABEL: orn8xi8: 86; CHECK: // %bb.0: 87; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b 88; CHECK-NEXT: ret 89 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > 90 %tmp2 = or <8 x i8> %a, %tmp1 91 ret <8 x i8> %tmp2 92} 93 94define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) { 95; CHECK-LABEL: orn16xi8: 96; CHECK: // %bb.0: 97; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b 98; CHECK-NEXT: ret 99 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > 100 %tmp2 = or <16 x i8> %a, %tmp1 101 ret <16 x i8> %tmp2 102} 103 104define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) { 105; CHECK-LABEL: bic8xi8: 106; CHECK: // %bb.0: 107; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b 108; CHECK-NEXT: ret 109 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > 110 %tmp2 = and <8 x i8> %a, %tmp1 111 ret <8 x i8> %tmp2 112} 113 114define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) { 115; CHECK-LABEL: bic16xi8: 116; CHECK: // %bb.0: 117; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b 118; CHECK-NEXT: ret 119 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > 120 %tmp2 = and <16 x i8> %a, %tmp1 121 ret <16 x i8> %tmp2 122} 123 124define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) { 125; CHECK-LABEL: orrimm2s_lsl0: 126; CHECK: // %bb.0: 127; CHECK-NEXT: orr v0.2s, #255 128; CHECK-NEXT: ret 129 %tmp1 = or <2 x i32> %a, < i32 255, i32 255> 130 ret <2 x i32> %tmp1 131} 132 133define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) { 134; CHECK-LABEL: orrimm2s_lsl8: 135; CHECK: // %bb.0: 136; CHECK-NEXT: orr v0.2s, #255, lsl #8 137; CHECK-NEXT: ret 138 %tmp1 = or <2 x i32> %a, < i32 65280, i32 65280> 139 ret <2 x i32> %tmp1 140} 141 142define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) { 143; CHECK-LABEL: orrimm2s_lsl16: 144; CHECK: // %bb.0: 145; CHECK-NEXT: orr v0.2s, #255, lsl #16 146; CHECK-NEXT: ret 147 %tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680> 148 ret <2 x i32> %tmp1 149} 150 151define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) { 152; CHECK-LABEL: orrimm2s_lsl24: 153; CHECK: // %bb.0: 154; CHECK-NEXT: orr v0.2s, #255, lsl #24 155; CHECK-NEXT: ret 156 %tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080> 157 ret <2 x i32> %tmp1 158} 159 160define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) { 161; CHECK-LABEL: orrimm4s_lsl0: 162; CHECK: // %bb.0: 163; CHECK-NEXT: orr v0.4s, #255 164; CHECK-NEXT: ret 165 %tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255> 166 ret <4 x i32> %tmp1 167} 168 169define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) { 170; CHECK-LABEL: orrimm4s_lsl8: 171; CHECK: // %bb.0: 172; CHECK-NEXT: orr v0.4s, #255, lsl #8 173; CHECK-NEXT: ret 174 %tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280> 175 ret <4 x i32> %tmp1 176} 177 178define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) { 179; CHECK-LABEL: orrimm4s_lsl16: 180; CHECK: // %bb.0: 181; CHECK-NEXT: orr v0.4s, #255, lsl #16 182; CHECK-NEXT: ret 183 %tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680> 184 ret <4 x i32> %tmp1 185} 186 187define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) { 188; CHECK-LABEL: orrimm4s_lsl24: 189; CHECK: // %bb.0: 190; CHECK-NEXT: orr v0.4s, #255, lsl #24 191; CHECK-NEXT: ret 192 %tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080> 193 ret <4 x i32> %tmp1 194} 195 196define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) { 197; CHECK-LABEL: orrimm4h_lsl0: 198; CHECK: // %bb.0: 199; CHECK-NEXT: orr v0.4h, #255 200; CHECK-NEXT: ret 201 %tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 > 202 ret <4 x i16> %tmp1 203} 204 205define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) { 206; CHECK-LABEL: orrimm4h_lsl8: 207; CHECK: // %bb.0: 208; CHECK-NEXT: orr v0.4h, #255, lsl #8 209; CHECK-NEXT: ret 210 %tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 > 211 ret <4 x i16> %tmp1 212} 213 214define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) { 215; CHECK-LABEL: orrimm8h_lsl0: 216; CHECK: // %bb.0: 217; CHECK-NEXT: orr v0.8h, #255 218; CHECK-NEXT: ret 219 %tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 > 220 ret <8 x i16> %tmp1 221} 222 223define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) { 224; CHECK-LABEL: orrimm8h_lsl8: 225; CHECK: // %bb.0: 226; CHECK-NEXT: orr v0.8h, #255, lsl #8 227; CHECK-NEXT: ret 228 %tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 > 229 ret <8 x i16> %tmp1 230} 231 232define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) { 233; CHECK-LABEL: bicimm2s_lsl0: 234; CHECK: // %bb.0: 235; CHECK-NEXT: bic v0.2s, #16 236; CHECK-NEXT: ret 237 %tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 > 238 ret <2 x i32> %tmp1 239} 240 241define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) { 242; CHECK-LABEL: bicimm2s_lsl8: 243; CHECK: // %bb.0: 244; CHECK-NEXT: bic v0.2s, #16, lsl #8 245; CHECK-NEXT: ret 246 %tmp1 = and <2 x i32> %a, < i32 4294963199, i32 4294963199 > 247 ret <2 x i32> %tmp1 248} 249 250define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) { 251; CHECK-LABEL: bicimm2s_lsl16: 252; CHECK: // %bb.0: 253; CHECK-NEXT: bic v0.2s, #16, lsl #16 254; CHECK-NEXT: ret 255 %tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 > 256 ret <2 x i32> %tmp1 257} 258 259define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) { 260; CHECK-LABEL: bicimm2s_lsl124: 261; CHECK: // %bb.0: 262; CHECK-NEXT: bic v0.2s, #16, lsl #24 263; CHECK-NEXT: ret 264 %tmp1 = and <2 x i32> %a, < i32 4026531839, i32 4026531839> 265 ret <2 x i32> %tmp1 266} 267 268define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) { 269; CHECK-LABEL: bicimm4s_lsl0: 270; CHECK: // %bb.0: 271; CHECK-NEXT: bic v0.4s, #16 272; CHECK-NEXT: ret 273 %tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 > 274 ret <4 x i32> %tmp1 275} 276 277define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) { 278; CHECK-LABEL: bicimm4s_lsl8: 279; CHECK: // %bb.0: 280; CHECK-NEXT: bic v0.4s, #16, lsl #8 281; CHECK-NEXT: ret 282 %tmp1 = and <4 x i32> %a, < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 > 283 ret <4 x i32> %tmp1 284} 285 286define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) { 287; CHECK-LABEL: bicimm4s_lsl16: 288; CHECK: // %bb.0: 289; CHECK-NEXT: bic v0.4s, #16, lsl #16 290; CHECK-NEXT: ret 291 %tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 > 292 ret <4 x i32> %tmp1 293} 294 295define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) { 296; CHECK-LABEL: bicimm4s_lsl124: 297; CHECK: // %bb.0: 298; CHECK-NEXT: bic v0.4s, #16, lsl #24 299; CHECK-NEXT: ret 300 %tmp1 = and <4 x i32> %a, < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839> 301 ret <4 x i32> %tmp1 302} 303 304define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) { 305; CHECK-LABEL: bicimm4h_lsl0_a: 306; CHECK: // %bb.0: 307; CHECK-NEXT: bic v0.4h, #16 308; CHECK-NEXT: ret 309 %tmp1 = and <4 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 > 310 ret <4 x i16> %tmp1 311} 312 313define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) { 314; CHECK-LABEL: bicimm4h_lsl0_b: 315; CHECK: // %bb.0: 316; CHECK-NEXT: bic v0.4h, #255 317; CHECK-NEXT: ret 318 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 > 319 ret <4 x i16> %tmp1 320} 321 322define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) { 323; CHECK-LABEL: bicimm4h_lsl8_a: 324; CHECK: // %bb.0: 325; CHECK-NEXT: bic v0.4h, #16, lsl #8 326; CHECK-NEXT: ret 327 %tmp1 = and <4 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199> 328 ret <4 x i16> %tmp1 329} 330 331define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) { 332; CHECK-LABEL: bicimm4h_lsl8_b: 333; CHECK: // %bb.0: 334; CHECK-NEXT: bic v0.4h, #255, lsl #8 335; CHECK-NEXT: ret 336 %tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255> 337 ret <4 x i16> %tmp1 338} 339 340define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) { 341; CHECK-LABEL: bicimm8h_lsl0_a: 342; CHECK: // %bb.0: 343; CHECK-NEXT: bic v0.8h, #16 344; CHECK-NEXT: ret 345 %tmp1 = and <8 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279, 346 i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 > 347 ret <8 x i16> %tmp1 348} 349 350define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) { 351; CHECK-LABEL: bicimm8h_lsl0_b: 352; CHECK: // %bb.0: 353; CHECK-NEXT: bic v0.8h, #255 354; CHECK-NEXT: ret 355 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 > 356 ret <8 x i16> %tmp1 357} 358 359define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) { 360; CHECK-LABEL: bicimm8h_lsl8_a: 361; CHECK: // %bb.0: 362; CHECK-NEXT: bic v0.8h, #16, lsl #8 363; CHECK-NEXT: ret 364 %tmp1 = and <8 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199, 365 i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199> 366 ret <8 x i16> %tmp1 367} 368 369define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) { 370; CHECK-LABEL: bicimm8h_lsl8_b: 371; CHECK: // %bb.0: 372; CHECK-NEXT: bic v0.8h, #255, lsl #8 373; CHECK-NEXT: ret 374 %tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> 375 ret <8 x i16> %tmp1 376} 377 378define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) { 379; CHECK-LABEL: and2xi32: 380; CHECK: // %bb.0: 381; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 382; CHECK-NEXT: ret 383 %tmp1 = and <2 x i32> %a, %b; 384 ret <2 x i32> %tmp1 385} 386 387define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) { 388; CHECK-LABEL: and4xi16: 389; CHECK: // %bb.0: 390; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 391; CHECK-NEXT: ret 392 %tmp1 = and <4 x i16> %a, %b; 393 ret <4 x i16> %tmp1 394} 395 396define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) { 397; CHECK-LABEL: and1xi64: 398; CHECK: // %bb.0: 399; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 400; CHECK-NEXT: ret 401 %tmp1 = and <1 x i64> %a, %b; 402 ret <1 x i64> %tmp1 403} 404 405define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) { 406; CHECK-LABEL: and4xi32: 407; CHECK: // %bb.0: 408; CHECK-NEXT: and v0.16b, v0.16b, v1.16b 409; CHECK-NEXT: ret 410 %tmp1 = and <4 x i32> %a, %b; 411 ret <4 x i32> %tmp1 412} 413 414define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) { 415; CHECK-LABEL: and8xi16: 416; CHECK: // %bb.0: 417; CHECK-NEXT: and v0.16b, v0.16b, v1.16b 418; CHECK-NEXT: ret 419 %tmp1 = and <8 x i16> %a, %b; 420 ret <8 x i16> %tmp1 421} 422 423define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) { 424; CHECK-LABEL: and2xi64: 425; CHECK: // %bb.0: 426; CHECK-NEXT: and v0.16b, v0.16b, v1.16b 427; CHECK-NEXT: ret 428 %tmp1 = and <2 x i64> %a, %b; 429 ret <2 x i64> %tmp1 430} 431 432define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) { 433; CHECK-LABEL: orr2xi32: 434; CHECK: // %bb.0: 435; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b 436; CHECK-NEXT: ret 437 %tmp1 = or <2 x i32> %a, %b; 438 ret <2 x i32> %tmp1 439} 440 441define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) { 442; CHECK-LABEL: orr4xi16: 443; CHECK: // %bb.0: 444; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b 445; CHECK-NEXT: ret 446 %tmp1 = or <4 x i16> %a, %b; 447 ret <4 x i16> %tmp1 448} 449 450define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) { 451; CHECK-LABEL: orr1xi64: 452; CHECK: // %bb.0: 453; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b 454; CHECK-NEXT: ret 455 %tmp1 = or <1 x i64> %a, %b; 456 ret <1 x i64> %tmp1 457} 458 459define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) { 460; CHECK-LABEL: orr4xi32: 461; CHECK: // %bb.0: 462; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 463; CHECK-NEXT: ret 464 %tmp1 = or <4 x i32> %a, %b; 465 ret <4 x i32> %tmp1 466} 467 468define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) { 469; CHECK-LABEL: orr8xi16: 470; CHECK: // %bb.0: 471; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 472; CHECK-NEXT: ret 473 %tmp1 = or <8 x i16> %a, %b; 474 ret <8 x i16> %tmp1 475} 476 477define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) { 478; CHECK-LABEL: orr2xi64: 479; CHECK: // %bb.0: 480; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 481; CHECK-NEXT: ret 482 %tmp1 = or <2 x i64> %a, %b; 483 ret <2 x i64> %tmp1 484} 485 486define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) { 487; CHECK-LABEL: eor2xi32: 488; CHECK: // %bb.0: 489; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b 490; CHECK-NEXT: ret 491 %tmp1 = xor <2 x i32> %a, %b; 492 ret <2 x i32> %tmp1 493} 494 495define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) { 496; CHECK-LABEL: eor4xi16: 497; CHECK: // %bb.0: 498; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b 499; CHECK-NEXT: ret 500 %tmp1 = xor <4 x i16> %a, %b; 501 ret <4 x i16> %tmp1 502} 503 504define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) { 505; CHECK-LABEL: eor1xi64: 506; CHECK: // %bb.0: 507; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b 508; CHECK-NEXT: ret 509 %tmp1 = xor <1 x i64> %a, %b; 510 ret <1 x i64> %tmp1 511} 512 513define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) { 514; CHECK-LABEL: eor4xi32: 515; CHECK: // %bb.0: 516; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b 517; CHECK-NEXT: ret 518 %tmp1 = xor <4 x i32> %a, %b; 519 ret <4 x i32> %tmp1 520} 521 522define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) { 523; CHECK-LABEL: eor8xi16: 524; CHECK: // %bb.0: 525; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b 526; CHECK-NEXT: ret 527 %tmp1 = xor <8 x i16> %a, %b; 528 ret <8 x i16> %tmp1 529} 530 531define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) { 532; CHECK-LABEL: eor2xi64: 533; CHECK: // %bb.0: 534; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b 535; CHECK-NEXT: ret 536 %tmp1 = xor <2 x i64> %a, %b; 537 ret <2 x i64> %tmp1 538} 539 540 541define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) { 542; CHECK-LABEL: bic2xi32: 543; CHECK: // %bb.0: 544; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b 545; CHECK-NEXT: ret 546 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 > 547 %tmp2 = and <2 x i32> %a, %tmp1 548 ret <2 x i32> %tmp2 549} 550 551define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) { 552; CHECK-LABEL: bic4xi16: 553; CHECK: // %bb.0: 554; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b 555; CHECK-NEXT: ret 556 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 > 557 %tmp2 = and <4 x i16> %a, %tmp1 558 ret <4 x i16> %tmp2 559} 560 561define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) { 562; CHECK-LABEL: bic1xi64: 563; CHECK: // %bb.0: 564; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b 565; CHECK-NEXT: ret 566 %tmp1 = xor <1 x i64> %b, < i64 -1> 567 %tmp2 = and <1 x i64> %a, %tmp1 568 ret <1 x i64> %tmp2 569} 570 571define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) { 572; CHECK-LABEL: bic4xi32: 573; CHECK: // %bb.0: 574; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b 575; CHECK-NEXT: ret 576 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1> 577 %tmp2 = and <4 x i32> %a, %tmp1 578 ret <4 x i32> %tmp2 579} 580 581define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) { 582; CHECK-LABEL: bic8xi16: 583; CHECK: // %bb.0: 584; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b 585; CHECK-NEXT: ret 586 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 > 587 %tmp2 = and <8 x i16> %a, %tmp1 588 ret <8 x i16> %tmp2 589} 590 591define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) { 592; CHECK-LABEL: bic2xi64: 593; CHECK: // %bb.0: 594; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b 595; CHECK-NEXT: ret 596 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1> 597 %tmp2 = and <2 x i64> %a, %tmp1 598 ret <2 x i64> %tmp2 599} 600 601define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) { 602; CHECK-LABEL: orn2xi32: 603; CHECK: // %bb.0: 604; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b 605; CHECK-NEXT: ret 606 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 > 607 %tmp2 = or <2 x i32> %a, %tmp1 608 ret <2 x i32> %tmp2 609} 610 611define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) { 612; CHECK-LABEL: orn4xi16: 613; CHECK: // %bb.0: 614; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b 615; CHECK-NEXT: ret 616 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 > 617 %tmp2 = or <4 x i16> %a, %tmp1 618 ret <4 x i16> %tmp2 619} 620 621define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) { 622; CHECK-LABEL: orn1xi64: 623; CHECK: // %bb.0: 624; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b 625; CHECK-NEXT: ret 626 %tmp1 = xor <1 x i64> %b, < i64 -1> 627 %tmp2 = or <1 x i64> %a, %tmp1 628 ret <1 x i64> %tmp2 629} 630 631define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) { 632; CHECK-LABEL: orn4xi32: 633; CHECK: // %bb.0: 634; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b 635; CHECK-NEXT: ret 636 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1> 637 %tmp2 = or <4 x i32> %a, %tmp1 638 ret <4 x i32> %tmp2 639} 640 641define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) { 642; CHECK-LABEL: orn8xi16: 643; CHECK: // %bb.0: 644; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b 645; CHECK-NEXT: ret 646 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 > 647 %tmp2 = or <8 x i16> %a, %tmp1 648 ret <8 x i16> %tmp2 649} 650 651define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) { 652; CHECK-LABEL: orn2xi64: 653; CHECK: // %bb.0: 654; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b 655; CHECK-NEXT: ret 656 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1> 657 %tmp2 = or <2 x i64> %a, %tmp1 658 ret <2 x i64> %tmp2 659} 660 661define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) { 662; CHECK-LABEL: bsl2xi32_const: 663; CHECK: // %bb.0: 664; CHECK-NEXT: movi d2, #0x000000ffffffff 665; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b 666; CHECK-NEXT: ret 667 %tmp1 = and <2 x i32> %a, < i32 -1, i32 0 > 668 %tmp2 = and <2 x i32> %b, < i32 0, i32 -1 > 669 %tmp3 = or <2 x i32> %tmp1, %tmp2 670 ret <2 x i32> %tmp3 671} 672 673 674define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) { 675; CHECK-LABEL: bsl4xi16_const: 676; CHECK: // %bb.0: 677; CHECK-NEXT: movi d2, #0x00ffff0000ffff 678; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b 679; CHECK-NEXT: ret 680 %tmp1 = and <4 x i16> %a, < i16 -1, i16 0, i16 -1,i16 0 > 681 %tmp2 = and <4 x i16> %b, < i16 0, i16 -1,i16 0, i16 -1 > 682 %tmp3 = or <4 x i16> %tmp1, %tmp2 683 ret <4 x i16> %tmp3 684} 685 686define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) { 687; CHECK-LABEL: bsl1xi64_const: 688; CHECK: // %bb.0: 689; CHECK-NEXT: movi d2, #0xffffffffffffff00 690; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b 691; CHECK-NEXT: ret 692 %tmp1 = and <1 x i64> %a, < i64 -256 > 693 %tmp2 = and <1 x i64> %b, < i64 255 > 694 %tmp3 = or <1 x i64> %tmp1, %tmp2 695 ret <1 x i64> %tmp3 696} 697 698define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) { 699; CHECK-LABEL: bsl4xi32_const: 700; CHECK: // %bb.0: 701; CHECK-NEXT: movi v2.2d, #0x000000ffffffff 702; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b 703; CHECK-NEXT: ret 704 %tmp1 = and <4 x i32> %a, < i32 -1, i32 0, i32 -1, i32 0 > 705 %tmp2 = and <4 x i32> %b, < i32 0, i32 -1, i32 0, i32 -1 > 706 %tmp3 = or <4 x i32> %tmp1, %tmp2 707 ret <4 x i32> %tmp3 708} 709 710define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) { 711; CHECK-LABEL: bsl8xi16_const: 712; CHECK: // %bb.0: 713; CHECK-NEXT: movi v2.2d, #0x000000ffffffff 714; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b 715; CHECK-NEXT: ret 716 %tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 0,i16 0, i16 -1, i16 -1, i16 0,i16 0 > 717 %tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 -1, i16 -1 > 718 %tmp3 = or <8 x i16> %tmp1, %tmp2 719 ret <8 x i16> %tmp3 720} 721 722define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) { 723; CHECK-LABEL: bsl2xi64_const: 724; CHECK: // %bb.0: 725; CHECK-NEXT: adrp x8, .LCPI75_0 726; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI75_0] 727; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b 728; CHECK-NEXT: ret 729 %tmp1 = and <2 x i64> %a, < i64 -1, i64 0 > 730 %tmp2 = and <2 x i64> %b, < i64 0, i64 -1 > 731 %tmp3 = or <2 x i64> %tmp1, %tmp2 732 ret <2 x i64> %tmp3 733} 734 735 736define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) { 737; CHECK-LABEL: bsl8xi8: 738; CHECK: // %bb.0: 739; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b 740; CHECK-NEXT: ret 741 %1 = and <8 x i8> %v1, %v2 742 %2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 743 %3 = and <8 x i8> %2, %v3 744 %4 = or <8 x i8> %1, %3 745 ret <8 x i8> %4 746} 747 748define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) { 749; CHECK-LABEL: bsl4xi16: 750; CHECK: // %bb.0: 751; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b 752; CHECK-NEXT: ret 753 %1 = and <4 x i16> %v1, %v2 754 %2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1> 755 %3 = and <4 x i16> %2, %v3 756 %4 = or <4 x i16> %1, %3 757 ret <4 x i16> %4 758} 759 760define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) { 761; CHECK-LABEL: bsl2xi32: 762; CHECK: // %bb.0: 763; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b 764; CHECK-NEXT: ret 765 %1 = and <2 x i32> %v1, %v2 766 %2 = xor <2 x i32> %v1, <i32 -1, i32 -1> 767 %3 = and <2 x i32> %2, %v3 768 %4 = or <2 x i32> %1, %3 769 ret <2 x i32> %4 770} 771 772define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) { 773; CHECK-LABEL: bsl1xi64: 774; CHECK: // %bb.0: 775; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b 776; CHECK-NEXT: ret 777 %1 = and <1 x i64> %v1, %v2 778 %2 = xor <1 x i64> %v1, <i64 -1> 779 %3 = and <1 x i64> %2, %v3 780 %4 = or <1 x i64> %1, %3 781 ret <1 x i64> %4 782} 783 784define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) { 785; CHECK-LABEL: bsl16xi8: 786; CHECK: // %bb.0: 787; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b 788; CHECK-NEXT: ret 789 %1 = and <16 x i8> %v1, %v2 790 %2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 791 %3 = and <16 x i8> %2, %v3 792 %4 = or <16 x i8> %1, %3 793 ret <16 x i8> %4 794} 795 796define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) { 797; CHECK-LABEL: bsl8xi16: 798; CHECK: // %bb.0: 799; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b 800; CHECK-NEXT: ret 801 %1 = and <8 x i16> %v1, %v2 802 %2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 803 %3 = and <8 x i16> %2, %v3 804 %4 = or <8 x i16> %1, %3 805 ret <8 x i16> %4 806} 807 808define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) { 809; CHECK-LABEL: bsl4xi32: 810; CHECK: // %bb.0: 811; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b 812; CHECK-NEXT: ret 813 %1 = and <4 x i32> %v1, %v2 814 %2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1> 815 %3 = and <4 x i32> %2, %v3 816 %4 = or <4 x i32> %1, %3 817 ret <4 x i32> %4 818} 819 820define <8 x i8> @vselect_v8i8(<8 x i8> %a) { 821; CHECK-LABEL: vselect_v8i8: 822; CHECK: // %bb.0: 823; CHECK-NEXT: movi d1, #0x0000000000ffff 824; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 825; CHECK-NEXT: orr v0.2s, #0 826; CHECK-NEXT: ret 827 %b = select <8 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> <i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 828 ret <8 x i8> %b 829} 830 831define <4 x i16> @vselect_v4i16(<4 x i16> %a) { 832; CHECK-LABEL: vselect_v4i16: 833; CHECK: // %bb.0: 834; CHECK-NEXT: movi d1, #0x0000000000ffff 835; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 836; CHECK-NEXT: orr v0.2s, #0 837; CHECK-NEXT: ret 838 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> %a, <4 x i16> <i16 undef, i16 0, i16 0, i16 0> 839 ret <4 x i16> %b 840} 841 842define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 843; CHECK-LABEL: vselect_cmp_ne: 844; CHECK: // %bb.0: 845; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b 846; CHECK-NEXT: bsl v0.8b, v2.8b, v1.8b 847; CHECK-NEXT: ret 848 %cmp = icmp ne <8 x i8> %a, %b 849 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c 850 ret <8 x i8> %d 851} 852 853define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 854; CHECK-LABEL: vselect_cmp_eq: 855; CHECK: // %bb.0: 856; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b 857; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b 858; CHECK-NEXT: ret 859 %cmp = icmp eq <8 x i8> %a, %b 860 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c 861 ret <8 x i8> %d 862} 863 864define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 865; CHECK-LABEL: vselect_cmpz_ne: 866; CHECK: // %bb.0: 867; CHECK-NEXT: cmeq v0.8b, v0.8b, #0 868; CHECK-NEXT: bsl v0.8b, v2.8b, v1.8b 869; CHECK-NEXT: ret 870 %cmp = icmp ne <8 x i8> %a, zeroinitializer 871 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c 872 ret <8 x i8> %d 873} 874 875define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 876; CHECK-LABEL: vselect_cmpz_eq: 877; CHECK: // %bb.0: 878; CHECK-NEXT: cmeq v0.8b, v0.8b, #0 879; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b 880; CHECK-NEXT: ret 881 %cmp = icmp eq <8 x i8> %a, zeroinitializer 882 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c 883 ret <8 x i8> %d 884} 885 886define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 887; CHECK-LABEL: vselect_tst: 888; CHECK: // %bb.0: 889; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 890; CHECK-NEXT: cmeq v0.8b, v0.8b, #0 891; CHECK-NEXT: bsl v0.8b, v2.8b, v1.8b 892; CHECK-NEXT: ret 893 %tmp3 = and <8 x i8> %a, %b 894 %tmp4 = icmp eq <8 x i8> %tmp3, zeroinitializer 895 %d = select <8 x i1> %tmp4, <8 x i8> %c, <8 x i8> %b 896 ret <8 x i8> %d 897} 898 899define <8 x i8> @sext_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 900; CHECK-LABEL: sext_tst: 901; CHECK: // %bb.0: 902; CHECK-NEXT: cmtst v0.8b, v0.8b, v1.8b 903; CHECK-NEXT: ret 904 %tmp3 = and <8 x i8> %a, %b 905 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer 906 %d = sext <8 x i1> %tmp4 to <8 x i8> 907 ret <8 x i8> %d 908} 909 910define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) { 911; CHECK-LABEL: bsl2xi64: 912; CHECK: // %bb.0: 913; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b 914; CHECK-NEXT: ret 915 %1 = and <2 x i64> %v1, %v2 916 %2 = xor <2 x i64> %v1, <i64 -1, i64 -1> 917 %3 = and <2 x i64> %2, %v3 918 %4 = or <2 x i64> %1, %3 919 ret <2 x i64> %4 920} 921 922define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) { 923; CHECK-LABEL: orrimm8b_as_orrimm4h_lsl0: 924; CHECK: // %bb.0: 925; CHECK-NEXT: orr v0.4h, #255 926; CHECK-NEXT: ret 927 %val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> 928 ret <8 x i8> %val 929} 930 931define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) { 932; CHECK-LABEL: orrimm8b_as_orimm4h_lsl8: 933; CHECK: // %bb.0: 934; CHECK-NEXT: orr v0.4h, #255, lsl #8 935; CHECK-NEXT: ret 936 %val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 937 ret <8 x i8> %val 938} 939 940define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) { 941; CHECK-LABEL: orimm16b_as_orrimm8h_lsl0: 942; CHECK: // %bb.0: 943; CHECK-NEXT: orr v0.8h, #255 944; CHECK-NEXT: ret 945 %val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> 946 ret <16 x i8> %val 947} 948 949define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) { 950; CHECK-LABEL: orimm16b_as_orrimm8h_lsl8: 951; CHECK: // %bb.0: 952; CHECK-NEXT: orr v0.8h, #255, lsl #8 953; CHECK-NEXT: ret 954 %val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 955 ret <16 x i8> %val 956} 957 958define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) { 959; CHECK-LABEL: and8imm2s_lsl0: 960; CHECK: // %bb.0: 961; CHECK-NEXT: bic v0.2s, #255 962; CHECK-NEXT: ret 963 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255> 964 ret <8 x i8> %tmp1 965} 966 967define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) { 968; CHECK-LABEL: and8imm2s_lsl8: 969; CHECK: // %bb.0: 970; CHECK-NEXT: bic v0.2s, #255, lsl #8 971; CHECK-NEXT: ret 972 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255> 973 ret <8 x i8> %tmp1 974} 975 976define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) { 977; CHECK-LABEL: and8imm2s_lsl16: 978; CHECK: // %bb.0: 979; CHECK-NEXT: bic v0.2s, #255, lsl #16 980; CHECK-NEXT: ret 981 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255> 982 ret <8 x i8> %tmp1 983} 984 985define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) { 986; CHECK-LABEL: and8imm2s_lsl24: 987; CHECK: // %bb.0: 988; CHECK-NEXT: bic v0.2s, #254, lsl #24 989; CHECK-NEXT: ret 990 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1> 991 ret <8 x i8> %tmp1 992} 993 994define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) { 995; CHECK-LABEL: and16imm2s_lsl0: 996; CHECK: // %bb.0: 997; CHECK-NEXT: bic v0.2s, #255 998; CHECK-NEXT: ret 999 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535> 1000 ret <4 x i16> %tmp1 1001} 1002 1003define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) { 1004; CHECK-LABEL: and16imm2s_lsl8: 1005; CHECK: // %bb.0: 1006; CHECK-NEXT: bic v0.2s, #255, lsl #8 1007; CHECK-NEXT: ret 1008 %tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535> 1009 ret <4 x i16> %tmp1 1010} 1011 1012define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) { 1013; CHECK-LABEL: and16imm2s_lsl16: 1014; CHECK: // %bb.0: 1015; CHECK-NEXT: bic v0.2s, #255, lsl #16 1016; CHECK-NEXT: ret 1017 %tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280> 1018 ret <4 x i16> %tmp1 1019} 1020 1021define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) { 1022; CHECK-LABEL: and16imm2s_lsl24: 1023; CHECK: // %bb.0: 1024; CHECK-NEXT: bic v0.2s, #254, lsl #24 1025; CHECK-NEXT: ret 1026 %tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511> 1027 ret <4 x i16> %tmp1 1028} 1029 1030 1031define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) { 1032; CHECK-LABEL: and64imm2s_lsl0: 1033; CHECK: // %bb.0: 1034; CHECK-NEXT: bic v0.2s, #255 1035; CHECK-NEXT: ret 1036 %tmp1 = and <1 x i64> %a, < i64 -1095216660736> 1037 ret <1 x i64> %tmp1 1038} 1039 1040define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) { 1041; CHECK-LABEL: and64imm2s_lsl8: 1042; CHECK: // %bb.0: 1043; CHECK-NEXT: bic v0.2s, #255, lsl #8 1044; CHECK-NEXT: ret 1045 %tmp1 = and <1 x i64> %a, < i64 -280375465148161> 1046 ret <1 x i64> %tmp1 1047} 1048 1049define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) { 1050; CHECK-LABEL: and64imm2s_lsl16: 1051; CHECK: // %bb.0: 1052; CHECK-NEXT: bic v0.2s, #255, lsl #16 1053; CHECK-NEXT: ret 1054 %tmp1 = and <1 x i64> %a, < i64 -71776119077928961> 1055 ret <1 x i64> %tmp1 1056} 1057 1058define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) { 1059; CHECK-LABEL: and64imm2s_lsl24: 1060; CHECK: // %bb.0: 1061; CHECK-NEXT: bic v0.2s, #254, lsl #24 1062; CHECK-NEXT: ret 1063 %tmp1 = and <1 x i64> %a, < i64 144115183814443007> 1064 ret <1 x i64> %tmp1 1065} 1066 1067define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) { 1068; CHECK-LABEL: and8imm4s_lsl0: 1069; CHECK: // %bb.0: 1070; CHECK-NEXT: bic v0.4s, #255 1071; CHECK-NEXT: ret 1072 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255> 1073 ret <16 x i8> %tmp1 1074} 1075 1076define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) { 1077; CHECK-LABEL: and8imm4s_lsl8: 1078; CHECK: // %bb.0: 1079; CHECK-NEXT: bic v0.4s, #255, lsl #8 1080; CHECK-NEXT: ret 1081 %tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255> 1082 ret <16 x i8> %tmp1 1083} 1084 1085define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) { 1086; CHECK-LABEL: and8imm4s_lsl16: 1087; CHECK: // %bb.0: 1088; CHECK-NEXT: bic v0.4s, #255, lsl #16 1089; CHECK-NEXT: ret 1090 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255> 1091 ret <16 x i8> %tmp1 1092} 1093 1094define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) { 1095; CHECK-LABEL: and8imm4s_lsl24: 1096; CHECK: // %bb.0: 1097; CHECK-NEXT: bic v0.4s, #254, lsl #24 1098; CHECK-NEXT: ret 1099 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1> 1100 ret <16 x i8> %tmp1 1101} 1102 1103define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) { 1104; CHECK-LABEL: and16imm4s_lsl0: 1105; CHECK: // %bb.0: 1106; CHECK-NEXT: bic v0.4s, #255 1107; CHECK-NEXT: ret 1108 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535> 1109 ret <8 x i16> %tmp1 1110} 1111 1112define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) { 1113; CHECK-LABEL: and16imm4s_lsl8: 1114; CHECK: // %bb.0: 1115; CHECK-NEXT: bic v0.4s, #255, lsl #8 1116; CHECK-NEXT: ret 1117 %tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535> 1118 ret <8 x i16> %tmp1 1119} 1120 1121define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) { 1122; CHECK-LABEL: and16imm4s_lsl16: 1123; CHECK: // %bb.0: 1124; CHECK-NEXT: bic v0.4s, #255, lsl #16 1125; CHECK-NEXT: ret 1126 %tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280> 1127 ret <8 x i16> %tmp1 1128} 1129 1130define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) { 1131; CHECK-LABEL: and16imm4s_lsl24: 1132; CHECK: // %bb.0: 1133; CHECK-NEXT: bic v0.4s, #254, lsl #24 1134; CHECK-NEXT: ret 1135 %tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511> 1136 ret <8 x i16> %tmp1 1137} 1138 1139define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) { 1140; CHECK-LABEL: and64imm4s_lsl0: 1141; CHECK: // %bb.0: 1142; CHECK-NEXT: bic v0.4s, #255 1143; CHECK-NEXT: ret 1144 %tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736> 1145 ret <2 x i64> %tmp1 1146} 1147 1148define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) { 1149; CHECK-LABEL: and64imm4s_lsl8: 1150; CHECK: // %bb.0: 1151; CHECK-NEXT: bic v0.4s, #255, lsl #8 1152; CHECK-NEXT: ret 1153 %tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161> 1154 ret <2 x i64> %tmp1 1155} 1156 1157define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) { 1158; CHECK-LABEL: and64imm4s_lsl16: 1159; CHECK: // %bb.0: 1160; CHECK-NEXT: bic v0.4s, #255, lsl #16 1161; CHECK-NEXT: ret 1162 %tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961> 1163 ret <2 x i64> %tmp1 1164} 1165 1166define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) { 1167; CHECK-LABEL: and64imm4s_lsl24: 1168; CHECK: // %bb.0: 1169; CHECK-NEXT: bic v0.4s, #254, lsl #24 1170; CHECK-NEXT: ret 1171 %tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007> 1172 ret <2 x i64> %tmp1 1173} 1174 1175define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) { 1176; CHECK-LABEL: and8imm4h_lsl0: 1177; CHECK: // %bb.0: 1178; CHECK-NEXT: bic v0.4h, #255 1179; CHECK-NEXT: ret 1180 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 1181 ret <8 x i8> %tmp1 1182} 1183 1184define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) { 1185; CHECK-LABEL: and8imm4h_lsl8: 1186; CHECK: // %bb.0: 1187; CHECK-NEXT: bic v0.4h, #255, lsl #8 1188; CHECK-NEXT: ret 1189 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> 1190 ret <8 x i8> %tmp1 1191} 1192 1193define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) { 1194; CHECK-LABEL: and16imm4h_lsl0: 1195; CHECK: // %bb.0: 1196; CHECK-NEXT: bic v0.4h, #255 1197; CHECK-NEXT: ret 1198 %tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360> 1199 ret <2 x i32> %tmp1 1200} 1201 1202define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) { 1203; CHECK-LABEL: and16imm4h_lsl8: 1204; CHECK: // %bb.0: 1205; CHECK-NEXT: bic v0.4h, #255, lsl #8 1206; CHECK-NEXT: ret 1207 %tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935> 1208 ret <2 x i32> %tmp1 1209} 1210 1211define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) { 1212; CHECK-LABEL: and64imm4h_lsl0: 1213; CHECK: // %bb.0: 1214; CHECK-NEXT: bic v0.4h, #255 1215; CHECK-NEXT: ret 1216 %tmp1 = and <1 x i64> %a, < i64 -71777214294589696> 1217 ret <1 x i64> %tmp1 1218} 1219 1220define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) { 1221; CHECK-LABEL: and64imm4h_lsl8: 1222; CHECK: // %bb.0: 1223; CHECK-NEXT: bic v0.4h, #255, lsl #8 1224; CHECK-NEXT: ret 1225 %tmp1 = and <1 x i64> %a, < i64 71777214294589695> 1226 ret <1 x i64> %tmp1 1227} 1228 1229define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) { 1230; CHECK-LABEL: and8imm8h_lsl0: 1231; CHECK: // %bb.0: 1232; CHECK-NEXT: bic v0.8h, #255 1233; CHECK-NEXT: ret 1234 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 > 1235 ret <16 x i8> %tmp1 1236} 1237 1238define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) { 1239; CHECK-LABEL: and8imm8h_lsl8: 1240; CHECK: // %bb.0: 1241; CHECK-NEXT: bic v0.8h, #255, lsl #8 1242; CHECK-NEXT: ret 1243 %tmp1 = and <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0 > 1244 ret <16 x i8> %tmp1 1245} 1246 1247define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) { 1248; CHECK-LABEL: and16imm8h_lsl0: 1249; CHECK: // %bb.0: 1250; CHECK-NEXT: bic v0.8h, #255 1251; CHECK-NEXT: ret 1252 %tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360> 1253 ret <4 x i32> %tmp1 1254} 1255 1256define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) { 1257; CHECK-LABEL: and16imm8h_lsl8: 1258; CHECK: // %bb.0: 1259; CHECK-NEXT: bic v0.8h, #255, lsl #8 1260; CHECK-NEXT: ret 1261 %tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935> 1262 ret <4 x i32> %tmp1 1263} 1264 1265define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) { 1266; CHECK-LABEL: and64imm8h_lsl0: 1267; CHECK: // %bb.0: 1268; CHECK-NEXT: bic v0.8h, #255 1269; CHECK-NEXT: ret 1270 %tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696> 1271 ret <2 x i64> %tmp1 1272} 1273 1274define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) { 1275; CHECK-LABEL: and64imm8h_lsl8: 1276; CHECK: // %bb.0: 1277; CHECK-NEXT: bic v0.8h, #255, lsl #8 1278; CHECK-NEXT: ret 1279 %tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695> 1280 ret <2 x i64> %tmp1 1281} 1282 1283define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) { 1284; CHECK-LABEL: orr8imm2s_lsl0: 1285; CHECK: // %bb.0: 1286; CHECK-NEXT: orr v0.2s, #255 1287; CHECK-NEXT: ret 1288 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0> 1289 ret <8 x i8> %tmp1 1290} 1291 1292define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) { 1293; CHECK-LABEL: orr8imm2s_lsl8: 1294; CHECK: // %bb.0: 1295; CHECK-NEXT: orr v0.2s, #255, lsl #8 1296; CHECK-NEXT: ret 1297 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0> 1298 ret <8 x i8> %tmp1 1299} 1300 1301define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) { 1302; CHECK-LABEL: orr8imm2s_lsl16: 1303; CHECK: // %bb.0: 1304; CHECK-NEXT: orr v0.2s, #255, lsl #16 1305; CHECK-NEXT: ret 1306 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0> 1307 ret <8 x i8> %tmp1 1308} 1309 1310define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) { 1311; CHECK-LABEL: orr8imm2s_lsl24: 1312; CHECK: // %bb.0: 1313; CHECK-NEXT: orr v0.2s, #255, lsl #24 1314; CHECK-NEXT: ret 1315 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255> 1316 ret <8 x i8> %tmp1 1317} 1318 1319define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) { 1320; CHECK-LABEL: orr16imm2s_lsl0: 1321; CHECK: // %bb.0: 1322; CHECK-NEXT: orr v0.2s, #255 1323; CHECK-NEXT: ret 1324 %tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0> 1325 ret <4 x i16> %tmp1 1326} 1327 1328define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) { 1329; CHECK-LABEL: orr16imm2s_lsl8: 1330; CHECK: // %bb.0: 1331; CHECK-NEXT: orr v0.2s, #255, lsl #8 1332; CHECK-NEXT: ret 1333 %tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0> 1334 ret <4 x i16> %tmp1 1335} 1336 1337define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) { 1338; CHECK-LABEL: orr16imm2s_lsl16: 1339; CHECK: // %bb.0: 1340; CHECK-NEXT: orr v0.2s, #255, lsl #16 1341; CHECK-NEXT: ret 1342 %tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255> 1343 ret <4 x i16> %tmp1 1344} 1345 1346define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) { 1347; CHECK-LABEL: orr16imm2s_lsl24: 1348; CHECK: // %bb.0: 1349; CHECK-NEXT: orr v0.2s, #255, lsl #24 1350; CHECK-NEXT: ret 1351 %tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280> 1352 ret <4 x i16> %tmp1 1353} 1354 1355define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) { 1356; CHECK-LABEL: orr64imm2s_lsl0: 1357; CHECK: // %bb.0: 1358; CHECK-NEXT: orr v0.2s, #255 1359; CHECK-NEXT: ret 1360 %tmp1 = or <1 x i64> %a, < i64 1095216660735> 1361 ret <1 x i64> %tmp1 1362} 1363 1364define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) { 1365; CHECK-LABEL: orr64imm2s_lsl8: 1366; CHECK: // %bb.0: 1367; CHECK-NEXT: orr v0.2s, #255, lsl #8 1368; CHECK-NEXT: ret 1369 %tmp1 = or <1 x i64> %a, < i64 280375465148160> 1370 ret <1 x i64> %tmp1 1371} 1372 1373define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) { 1374; CHECK-LABEL: orr64imm2s_lsl16: 1375; CHECK: // %bb.0: 1376; CHECK-NEXT: orr v0.2s, #255, lsl #16 1377; CHECK-NEXT: ret 1378 %tmp1 = or <1 x i64> %a, < i64 71776119077928960> 1379 ret <1 x i64> %tmp1 1380} 1381 1382define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) { 1383; CHECK-LABEL: orr64imm2s_lsl24: 1384; CHECK: // %bb.0: 1385; CHECK-NEXT: orr v0.2s, #255, lsl #24 1386; CHECK-NEXT: ret 1387 %tmp1 = or <1 x i64> %a, < i64 -72057589759737856> 1388 ret <1 x i64> %tmp1 1389} 1390 1391define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) { 1392; CHECK-LABEL: orr8imm4s_lsl0: 1393; CHECK: // %bb.0: 1394; CHECK-NEXT: orr v0.4s, #255 1395; CHECK-NEXT: ret 1396 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0> 1397 ret <16 x i8> %tmp1 1398} 1399 1400define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) { 1401; CHECK-LABEL: orr8imm4s_lsl8: 1402; CHECK: // %bb.0: 1403; CHECK-NEXT: orr v0.4s, #255, lsl #8 1404; CHECK-NEXT: ret 1405 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0> 1406 ret <16 x i8> %tmp1 1407} 1408 1409define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) { 1410; CHECK-LABEL: orr8imm4s_lsl16: 1411; CHECK: // %bb.0: 1412; CHECK-NEXT: orr v0.4s, #255, lsl #16 1413; CHECK-NEXT: ret 1414 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0> 1415 ret <16 x i8> %tmp1 1416} 1417 1418define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) { 1419; CHECK-LABEL: orr8imm4s_lsl24: 1420; CHECK: // %bb.0: 1421; CHECK-NEXT: orr v0.4s, #255, lsl #24 1422; CHECK-NEXT: ret 1423 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255> 1424 ret <16 x i8> %tmp1 1425} 1426 1427define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) { 1428; CHECK-LABEL: orr16imm4s_lsl0: 1429; CHECK: // %bb.0: 1430; CHECK-NEXT: orr v0.4s, #255 1431; CHECK-NEXT: ret 1432 %tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0> 1433 ret <8 x i16> %tmp1 1434} 1435 1436define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) { 1437; CHECK-LABEL: orr16imm4s_lsl8: 1438; CHECK: // %bb.0: 1439; CHECK-NEXT: orr v0.4s, #255, lsl #8 1440; CHECK-NEXT: ret 1441 %tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0> 1442 ret <8 x i16> %tmp1 1443} 1444 1445define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) { 1446; CHECK-LABEL: orr16imm4s_lsl16: 1447; CHECK: // %bb.0: 1448; CHECK-NEXT: orr v0.4s, #255, lsl #16 1449; CHECK-NEXT: ret 1450 %tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255> 1451 ret <8 x i16> %tmp1 1452} 1453 1454define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) { 1455; CHECK-LABEL: orr16imm4s_lsl24: 1456; CHECK: // %bb.0: 1457; CHECK-NEXT: orr v0.4s, #255, lsl #24 1458; CHECK-NEXT: ret 1459 %tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280> 1460 ret <8 x i16> %tmp1 1461} 1462 1463define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) { 1464; CHECK-LABEL: orr64imm4s_lsl0: 1465; CHECK: // %bb.0: 1466; CHECK-NEXT: orr v0.4s, #255 1467; CHECK-NEXT: ret 1468 %tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735> 1469 ret <2 x i64> %tmp1 1470} 1471 1472define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) { 1473; CHECK-LABEL: orr64imm4s_lsl8: 1474; CHECK: // %bb.0: 1475; CHECK-NEXT: orr v0.4s, #255, lsl #8 1476; CHECK-NEXT: ret 1477 %tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160> 1478 ret <2 x i64> %tmp1 1479} 1480 1481define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) { 1482; CHECK-LABEL: orr64imm4s_lsl16: 1483; CHECK: // %bb.0: 1484; CHECK-NEXT: orr v0.4s, #255, lsl #16 1485; CHECK-NEXT: ret 1486 %tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960> 1487 ret <2 x i64> %tmp1 1488} 1489 1490define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) { 1491; CHECK-LABEL: orr64imm4s_lsl24: 1492; CHECK: // %bb.0: 1493; CHECK-NEXT: orr v0.4s, #255, lsl #24 1494; CHECK-NEXT: ret 1495 %tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856> 1496 ret <2 x i64> %tmp1 1497} 1498 1499define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) { 1500; CHECK-LABEL: orr8imm4h_lsl0: 1501; CHECK: // %bb.0: 1502; CHECK-NEXT: orr v0.4h, #255 1503; CHECK-NEXT: ret 1504 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> 1505 ret <8 x i8> %tmp1 1506} 1507 1508define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) { 1509; CHECK-LABEL: orr8imm4h_lsl8: 1510; CHECK: // %bb.0: 1511; CHECK-NEXT: orr v0.4h, #255, lsl #8 1512; CHECK-NEXT: ret 1513 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 1514 ret <8 x i8> %tmp1 1515} 1516 1517define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) { 1518; CHECK-LABEL: orr16imm4h_lsl0: 1519; CHECK: // %bb.0: 1520; CHECK-NEXT: orr v0.4h, #255 1521; CHECK-NEXT: ret 1522 %tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935> 1523 ret <2 x i32> %tmp1 1524} 1525 1526define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) { 1527; CHECK-LABEL: orr16imm4h_lsl8: 1528; CHECK: // %bb.0: 1529; CHECK-NEXT: orr v0.4h, #255, lsl #8 1530; CHECK-NEXT: ret 1531 %tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360> 1532 ret <2 x i32> %tmp1 1533} 1534 1535define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) { 1536; CHECK-LABEL: orr64imm4h_lsl0: 1537; CHECK: // %bb.0: 1538; CHECK-NEXT: orr v0.4h, #255 1539; CHECK-NEXT: ret 1540 %tmp1 = or <1 x i64> %a, < i64 71777214294589695> 1541 ret <1 x i64> %tmp1 1542} 1543 1544define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) { 1545; CHECK-LABEL: orr64imm4h_lsl8: 1546; CHECK: // %bb.0: 1547; CHECK-NEXT: orr v0.4h, #255, lsl #8 1548; CHECK-NEXT: ret 1549 %tmp1 = or <1 x i64> %a, < i64 -71777214294589696> 1550 ret <1 x i64> %tmp1 1551} 1552 1553define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) { 1554; CHECK-LABEL: orr8imm8h_lsl0: 1555; CHECK: // %bb.0: 1556; CHECK-NEXT: orr v0.8h, #255 1557; CHECK-NEXT: ret 1558 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> 1559 ret <16 x i8> %tmp1 1560} 1561 1562define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) { 1563; CHECK-LABEL: orr8imm8h_lsl8: 1564; CHECK: // %bb.0: 1565; CHECK-NEXT: orr v0.8h, #255, lsl #8 1566; CHECK-NEXT: ret 1567 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 1568 ret <16 x i8> %tmp1 1569} 1570 1571define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) { 1572; CHECK-LABEL: orr16imm8h_lsl0: 1573; CHECK: // %bb.0: 1574; CHECK-NEXT: orr v0.8h, #255 1575; CHECK-NEXT: ret 1576 %tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935> 1577 ret <4 x i32> %tmp1 1578} 1579 1580define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) { 1581; CHECK-LABEL: orr16imm8h_lsl8: 1582; CHECK: // %bb.0: 1583; CHECK-NEXT: orr v0.8h, #255, lsl #8 1584; CHECK-NEXT: ret 1585 %tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360> 1586 ret <4 x i32> %tmp1 1587} 1588 1589define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) { 1590; CHECK-LABEL: orr64imm8h_lsl0: 1591; CHECK: // %bb.0: 1592; CHECK-NEXT: orr v0.8h, #255 1593; CHECK-NEXT: ret 1594 %tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695> 1595 ret <2 x i64> %tmp1 1596} 1597 1598define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) { 1599; CHECK-LABEL: orr64imm8h_lsl8: 1600; CHECK: // %bb.0: 1601; CHECK-NEXT: orr v0.8h, #255, lsl #8 1602; CHECK-NEXT: ret 1603 %tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696> 1604 ret <2 x i64> %tmp1 1605} 1606 1607