1; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s 2; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 3 4target triple = "aarch64-unknown-linux-gnu" 5 6; Currently there is no custom lowering for vector shuffles operating on types 7; bigger than NEON. However, having no support opens us up to a code generator 8; hang when expanding BUILD_VECTOR. Here we just validate the promblematic case 9; successfully exits code generation. 10define void @hang_when_merging_stores_after_legalisation(<8 x i32>* %a, <2 x i32> %b) #0 { 11; CHECK-LABEL: hang_when_merging_stores_after_legalisation: 12 %splat = shufflevector <2 x i32> %b, <2 x i32> undef, <8 x i32> zeroinitializer 13 %interleaved.vec = shufflevector <8 x i32> %splat, <8 x i32> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> 14 store <8 x i32> %interleaved.vec, <8 x i32>* %a, align 4 15 ret void 16} 17 18; NOTE: Currently all CONCAT_VECTORS get expanded so there's little point in 19; validating all combinations of vector type. 20 21define void @concat_vectors_v4i64(<2 x i64> %a, <2 x i64> %b, <4 x i64> *%c.addr) #0 { 22; CHECK-LABEL: concat_vectors_v4i64: 23; CHECK: stp q0, q1, [sp] 24; CHECK: ptrue [[OUT_PG:p[0-9]+]].d, vl4 25; CHECK: mov x[[LO_ADDR:[0-9]+]], sp 26; CHECK: ld1d { z{{[0-9]+}}.d }, [[OUT_PG]]/z, [x[[LO_ADDR]]] 27 %concat = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 28 store <4 x i64> %concat, <4 x i64>* %c.addr 29 ret void 30} 31 32define void @concat_vectors_v8i64(<4 x i64> *%a.addr, <4 x i64> *%b.addr, <8 x i64> *%c.addr) #0 { 33; VBITS_GE_512-LABEL: concat_vectors_v8i64: 34; VBITS_GE_512: ptrue [[IN_PG:p[0-9]+]].d, vl4 35; VBITS_GE_512: ld1d { [[LO:z[0-9]+]].d }, [[IN_PG]]/z, [x0] 36; VBITS_GE_512: ld1d { [[HI:z[0-9]+]].d }, [[IN_PG]]/z, [x1] 37; VBITS_GE_512: mov x[[LO_ADDR:[0-9]+]], sp 38; VBITS_GE_512: orr x[[HI_ADDR:[0-9]+]], x[[LO_ADDR]], #0x20 39; VBITS_GE_512: st1d { [[LO]].d }, [[IN_PG]], [x[[LO_ADDR]]] 40; VBITS_GE_512: st1d { [[HI]].d }, [[IN_PG]], [x[[HI_ADDR]]] 41; VBITS_GE_512: ptrue [[OUT_PG:p[0-9]+]].d, vl8 42; VBITS_GE_512: ld1d { z{{[0-9]+}}.d }, [[OUT_PG]]/z, [x8] 43 %a = load <4 x i64>, <4 x i64>* %a.addr 44 %b = load <4 x i64>, <4 x i64>* %b.addr 45 %concat = shufflevector <4 x i64> %a, <4 x i64> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 46 store <8 x i64> %concat, <8 x i64>* %c.addr 47 ret void 48} 49 50attributes #0 = { nounwind "target-features"="+sve" } 51