1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s 2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 3 4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 5; WARN-NOT: warning 6 7; Verify that DAG combine rules for LD1 + sext/zext don't apply when the 8; result of LD1 has multiple uses 9 10define <vscale x 2 x i64> @no_dag_combine_zext_sext(<vscale x 2 x i1> %pg, 11 <vscale x 2 x i64> %base, 12 <vscale x 2 x i8>* %res_out, 13 <vscale x 2 x i1> %pred) { 14; CHECK-LABEL: no_dag_combine_zext_sext 15; CHECK: ld1b { z0.d }, p0/z, [z0.d, #16] 16; CHECK-NEXT: st1b { z0.d }, p1, [x0] 17; CHECK-NEXT: and z0.d, z0.d, #0xff 18; CHECK-NEXT: ret 19 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i1> %pg, 20 <vscale x 2 x i64> %base, 21 i64 16) 22 %res1 = zext <vscale x 2 x i8> %load to <vscale x 2 x i64> 23 %res2 = sext <vscale x 2 x i8> %load to <vscale x 2 x i64> 24 call void @llvm.masked.store.nxv2i8(<vscale x 2 x i8> %load, 25 <vscale x 2 x i8> *%res_out, 26 i32 8, 27 <vscale x 2 x i1> %pred) 28 29 ret <vscale x 2 x i64> %res1 30} 31 32define <vscale x 2 x i64> @no_dag_combine_sext(<vscale x 2 x i1> %pg, 33 <vscale x 2 x i64> %base, 34 <vscale x 2 x i8>* %res_out, 35 <vscale x 2 x i1> %pred) { 36; CHECK-LABEL: no_dag_combine_sext 37; CHECK: ld1b { z1.d }, p0/z, [z0.d, #16] 38; CHECK-NEXT: ptrue p0.d 39; CHECK-NEXT: sxtb z0.d, p0/m, z1.d 40; CHECK-NEXT: st1b { z1.d }, p1, [x0] 41; CHECK-NEXT: ret 42 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i1> %pg, 43 <vscale x 2 x i64> %base, 44 i64 16) 45 %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64> 46 call void @llvm.masked.store.nxv2i8(<vscale x 2 x i8> %load, 47 <vscale x 2 x i8> *%res_out, 48 i32 8, 49 <vscale x 2 x i1> %pred) 50 51 ret <vscale x 2 x i64> %res 52} 53 54define <vscale x 2 x i64> @no_dag_combine_zext(<vscale x 2 x i1> %pg, 55 <vscale x 2 x i64> %base, 56 <vscale x 2 x i8>* %res_out, 57 <vscale x 2 x i1> %pred) { 58; CHECK-LABEL: no_dag_combine_zext 59; CHECK: ld1b { z0.d }, p0/z, [z0.d, #16] 60; CHECK-NEXT: st1b { z0.d }, p1, [x0] 61; CHECK-NEXT: and z0.d, z0.d, #0xff 62; CHECK-NEXT: ret 63 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i1> %pg, 64 <vscale x 2 x i64> %base, 65 i64 16) 66 %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64> 67 call void @llvm.masked.store.nxv2i8(<vscale x 2 x i8> %load, 68 <vscale x 2 x i8> *%res_out, 69 i32 8, 70 <vscale x 2 x i1> %pred) 71 72 ret <vscale x 2 x i64> %res 73} 74 75declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) 76declare void @llvm.masked.store.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>*, i32, <vscale x 2 x i1>) 77