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1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
3
4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
5; WARN-NOT: warning
6
7;
8; SMAX
9;
10define <vscale x 16 x i8> @smax_i8_pos(<vscale x 16 x i8> %a) {
11; CHECK-LABEL: smax_i8_pos
12; CHECK: smax z0.b, z0.b, #27
13; CHECK-NEXT: ret
14  %elt = insertelement <vscale x 16 x i8> undef, i8 27, i32 0
15  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
16  %cmp = icmp sgt <vscale x 16 x i8> %a, %splat
17  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %splat
18  ret <vscale x 16 x i8> %res
19}
20
21define <vscale x 16 x i8> @smax_i8_neg(<vscale x 16 x i8> %a) {
22; CHECK-LABEL: smax_i8_neg
23; CHECK: smax z0.b, z0.b, #-58
24; CHECK-NEXT: ret
25  %elt = insertelement <vscale x 16 x i8> undef, i8 -58, i32 0
26  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
27  %cmp = icmp sgt <vscale x 16 x i8> %a, %splat
28  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %splat
29  ret <vscale x 16 x i8> %res
30}
31
32define <vscale x 8 x i16> @smax_i16_pos(<vscale x 8 x i16> %a) {
33; CHECK-LABEL: smax_i16_pos
34; CHECK: smax z0.h, z0.h, #27
35; CHECK-NEXT: ret
36  %elt = insertelement <vscale x 8 x i16> undef, i16 27, i32 0
37  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
38  %cmp = icmp sgt <vscale x 8 x i16> %a, %splat
39  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %splat
40  ret <vscale x 8 x i16> %res
41}
42
43define <vscale x 8 x i16> @smax_i16_neg(<vscale x 8 x i16> %a) {
44; CHECK-LABEL: smax_i16_neg
45; CHECK: smax z0.h, z0.h, #-58
46; CHECK-NEXT: ret
47  %elt = insertelement <vscale x 8 x i16> undef, i16 -58, i32 0
48  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
49  %cmp = icmp sgt <vscale x 8 x i16> %a, %splat
50  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %splat
51  ret <vscale x 8 x i16> %res
52}
53
54define <vscale x 8 x i16> @smax_i16_out_of_range(<vscale x 8 x i16> %a) {
55; CHECK-LABEL: smax_i16_out_of_range:
56; CHECK:    mov w8, #257
57; CHECK-NEXT:    mov z1.h, w8
58; CHECK-NEXT:    ptrue p0.h
59; CHECK-NEXT:    smax z0.h, p0/m, z0.h, z1.h
60; CHECK-NEXT:    ret
61  %elt = insertelement <vscale x 8 x i16> undef, i16 257, i32 0
62  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
63  %cmp = icmp sgt <vscale x 8 x i16> %a, %splat
64  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %splat
65  ret <vscale x 8 x i16> %res
66}
67
68define <vscale x 4 x i32> @smax_i32_pos(<vscale x 4 x i32> %a) {
69; CHECK-LABEL: smax_i32_pos
70; CHECK: smax z0.s, z0.s, #27
71; CHECK: ret
72  %elt = insertelement <vscale x 4 x i32> undef, i32 27, i32 0
73  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
74  %cmp = icmp sgt <vscale x 4 x i32> %a, %splat
75  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %splat
76  ret <vscale x 4 x i32> %res
77}
78
79define <vscale x 4 x i32> @smax_i32_neg(<vscale x 4 x i32> %a) {
80; CHECK-LABEL: smax_i32_neg
81; CHECK: smax z0.s, z0.s, #-58
82; CHECK-NEXT: ret
83  %elt = insertelement <vscale x 4 x i32> undef, i32 -58, i32 0
84  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
85  %cmp = icmp sgt <vscale x 4 x i32> %a, %splat
86  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %splat
87  ret <vscale x 4 x i32> %res
88}
89
90define <vscale x 4 x i32> @smax_i32_out_of_range(<vscale x 4 x i32> %a) {
91; CHECK-LABEL: smax_i32_out_of_range:
92; CHECK:    mov w8, #-129
93; CHECK-NEXT:    mov z1.s, w8
94; CHECK-NEXT:    ptrue p0.s
95; CHECK-NEXT:    smax z0.s, p0/m, z0.s, z1.s
96; CHECK-NEXT:    ret
97  %elt = insertelement <vscale x 4 x i32> undef, i32 -129, i32 0
98  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
99  %cmp = icmp sgt <vscale x 4 x i32> %a, %splat
100  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %splat
101  ret <vscale x 4 x i32> %res
102}
103
104define <vscale x 2 x i64> @smax_i64_pos(<vscale x 2 x i64> %a) {
105; CHECK-LABEL: smax_i64_pos
106; CHECK: smax z0.d, z0.d, #27
107; CHECK-NEXT: ret
108  %elt = insertelement <vscale x 2 x i64> undef, i64 27, i32 0
109  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
110  %cmp = icmp sgt <vscale x 2 x i64> %a, %splat
111  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %splat
112  ret <vscale x 2 x i64> %res
113}
114
115define <vscale x 2 x i64> @smax_i64_neg(<vscale x 2 x i64> %a) {
116; CHECK-LABEL: smax_i64_neg
117; CHECK: smax z0.d, z0.d, #-58
118; CHECK-NEXT: ret
119  %elt = insertelement <vscale x 2 x i64> undef, i64 -58, i32 0
120  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
121  %cmp = icmp sgt <vscale x 2 x i64> %a, %splat
122  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %splat
123  ret <vscale x 2 x i64> %res
124}
125
126define <vscale x 2 x i64> @smax_i64_out_of_range(<vscale x 2 x i64> %a) {
127; CHECK-LABEL: smax_i64_out_of_range:
128; CHECK:    mov w8, #65535
129; CHECK-NEXT:    mov z1.d, x8
130; CHECK-NEXT:    ptrue p0.d
131; CHECK-NEXT:    smax z0.d, p0/m, z0.d, z1.d
132; CHECK-NEXT:    ret
133  %elt = insertelement <vscale x 2 x i64> undef, i64 65535, i32 0
134  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
135  %cmp = icmp sgt <vscale x 2 x i64> %a, %splat
136  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %splat
137  ret <vscale x 2 x i64> %res
138}
139
140;
141; SMIN
142;
143define <vscale x 16 x i8> @smin_i8_pos(<vscale x 16 x i8> %a) {
144; CHECK-LABEL: smin_i8_pos
145; CHECK: smin z0.b, z0.b, #27
146; CHECK-NEXT: ret
147  %elt = insertelement <vscale x 16 x i8> undef, i8 27, i32 0
148  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
149  %cmp = icmp slt <vscale x 16 x i8> %a, %splat
150  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %splat
151  ret <vscale x 16 x i8> %res
152}
153
154define <vscale x 16 x i8> @smin_i8_neg(<vscale x 16 x i8> %a) {
155; CHECK-LABEL: smin_i8_neg
156; CHECK: smin z0.b, z0.b, #-58
157; CHECK-NEXT: ret
158  %elt = insertelement <vscale x 16 x i8> undef, i8 -58, i32 0
159  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
160  %cmp = icmp slt <vscale x 16 x i8> %a, %splat
161  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %splat
162  ret <vscale x 16 x i8> %res
163}
164
165define <vscale x 8 x i16> @smin_i16_pos(<vscale x 8 x i16> %a) {
166; CHECK-LABEL: smin_i16_pos
167; CHECK: smin z0.h, z0.h, #27
168; CHECK-NEXT: ret
169  %elt = insertelement <vscale x 8 x i16> undef, i16 27, i32 0
170  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
171  %cmp = icmp slt <vscale x 8 x i16> %a, %splat
172  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %splat
173  ret <vscale x 8 x i16> %res
174}
175
176define <vscale x 8 x i16> @smin_i16_neg(<vscale x 8 x i16> %a) {
177; CHECK-LABEL: smin_i16_neg
178; CHECK: smin z0.h, z0.h, #-58
179; CHECK-NEXT: ret
180  %elt = insertelement <vscale x 8 x i16> undef, i16 -58, i32 0
181  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
182  %cmp = icmp slt <vscale x 8 x i16> %a, %splat
183  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %splat
184  ret <vscale x 8 x i16> %res
185}
186
187define <vscale x 8 x i16> @smin_i16_out_of_range(<vscale x 8 x i16> %a) {
188; CHECK-LABEL: smin_i16_out_of_range:
189; CHECK:    mov w8, #257
190; CHECK-NEXT:    mov z1.h, w8
191; CHECK-NEXT:    ptrue p0.h
192; CHECK-NEXT:    smin z0.h, p0/m, z0.h, z1.h
193; CHECK-NEXT:    ret
194  %elt = insertelement <vscale x 8 x i16> undef, i16 257, i32 0
195  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
196  %cmp = icmp slt <vscale x 8 x i16> %a, %splat
197  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %splat
198  ret <vscale x 8 x i16> %res
199}
200
201define <vscale x 4 x i32> @smin_i32_pos(<vscale x 4 x i32> %a) {
202; CHECK-LABEL: smin_i32_pos
203; CHECK: smin z0.s, z0.s, #27
204; CHECK-NEXT: ret
205  %elt = insertelement <vscale x 4 x i32> undef, i32 27, i32 0
206  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
207  %cmp = icmp slt <vscale x 4 x i32> %a, %splat
208  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %splat
209  ret <vscale x 4 x i32> %res
210}
211
212define <vscale x 4 x i32> @smin_i32_neg(<vscale x 4 x i32> %a) {
213; CHECK-LABEL: smin_i32_neg
214; CHECK: smin z0.s, z0.s, #-58
215; CHECK-NEXT: ret
216  %elt = insertelement <vscale x 4 x i32> undef, i32 -58, i32 0
217  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
218  %cmp = icmp slt <vscale x 4 x i32> %a, %splat
219  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %splat
220  ret <vscale x 4 x i32> %res
221}
222
223define <vscale x 4 x i32> @smin_i32_out_of_range(<vscale x 4 x i32> %a) {
224; CHECK-LABEL: smin_i32_out_of_range:
225; CHECK:    mov w8, #-129
226; CHECK-NEXT:    mov z1.s, w8
227; CHECK-NEXT:    ptrue p0.s
228; CHECK-NEXT:    smin z0.s, p0/m, z0.s, z1.s
229; CHECK-NEXT:    ret
230  %elt = insertelement <vscale x 4 x i32> undef, i32 -129, i32 0
231  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
232  %cmp = icmp slt <vscale x 4 x i32> %a, %splat
233  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %splat
234  ret <vscale x 4 x i32> %res
235}
236
237define <vscale x 2 x i64> @smin_i64_pos(<vscale x 2 x i64> %a) {
238; CHECK-LABEL: smin_i64_pos
239; CHECK: smin z0.d, z0.d, #27
240; CHECK-NEXT: ret
241  %elt = insertelement <vscale x 2 x i64> undef, i64 27, i32 0
242  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
243  %cmp = icmp slt <vscale x 2 x i64> %a, %splat
244  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %splat
245  ret <vscale x 2 x i64> %res
246}
247
248define <vscale x 2 x i64> @smin_i64_neg(<vscale x 2 x i64> %a) {
249; CHECK-LABEL: smin_i64_neg
250; CHECK: smin z0.d, z0.d, #-58
251; CHECK-NEXT: ret
252  %elt = insertelement <vscale x 2 x i64> undef, i64 -58, i32 0
253  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
254  %cmp = icmp slt <vscale x 2 x i64> %a, %splat
255  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %splat
256  ret <vscale x 2 x i64> %res
257}
258
259define <vscale x 2 x i64> @smin_i64_out_of_range(<vscale x 2 x i64> %a) {
260; CHECK-LABEL: smin_i64_out_of_range:
261; CHECK:    mov w8, #65535
262; CHECK-NEXT:    mov z1.d, x8
263; CHECK-NEXT:    ptrue p0.d
264; CHECK-NEXT:    smin z0.d, p0/m, z0.d, z1.d
265; CHECK-NEXT:    ret
266  %elt = insertelement <vscale x 2 x i64> undef, i64 65535, i32 0
267  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
268  %cmp = icmp slt <vscale x 2 x i64> %a, %splat
269  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %splat
270  ret <vscale x 2 x i64> %res
271}
272
273;
274; UMAX
275;
276define <vscale x 16 x i8> @umax_i8_pos(<vscale x 16 x i8> %a) {
277; CHECK-LABEL: umax_i8_pos
278; CHECK: umax z0.b, z0.b, #27
279; CHECK-NEXT: ret
280  %elt = insertelement <vscale x 16 x i8> undef, i8 27, i32 0
281  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
282  %cmp = icmp ugt <vscale x 16 x i8> %a, %splat
283  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %splat
284  ret <vscale x 16 x i8> %res
285}
286
287define <vscale x 16 x i8> @umax_i8_large(<vscale x 16 x i8> %a) {
288; CHECK-LABEL: umax_i8_large
289; CHECK: umax z0.b, z0.b, #129
290; CHECK-NEXT: ret
291  %elt = insertelement <vscale x 16 x i8> undef, i8 129, i32 0
292  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
293  %cmp = icmp ugt <vscale x 16 x i8> %a, %splat
294  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %splat
295  ret <vscale x 16 x i8> %res
296}
297
298define <vscale x 8 x i16> @umax_i16_pos(<vscale x 8 x i16> %a) {
299; CHECK-LABEL: umax_i16_pos
300; CHECK: umax z0.h, z0.h, #27
301; CHECK-NEXT: ret
302  %elt = insertelement <vscale x 8 x i16> undef, i16 27, i32 0
303  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
304  %cmp = icmp ugt <vscale x 8 x i16> %a, %splat
305  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %splat
306  ret <vscale x 8 x i16> %res
307}
308
309define <vscale x 8 x i16> @umax_i16_out_of_range(<vscale x 8 x i16> %a) {
310; CHECK-LABEL: umax_i16_out_of_range:
311; CHECK:    mov w8, #257
312; CHECK-NEXT:    mov z1.h, w8
313; CHECK-NEXT:    ptrue p0.h
314; CHECK-NEXT:    umax z0.h, p0/m, z0.h, z1.h
315; CHECK-NEXT:    ret
316  %elt = insertelement <vscale x 8 x i16> undef, i16 257, i32 0
317  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
318  %cmp = icmp ugt <vscale x 8 x i16> %a, %splat
319  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %splat
320  ret <vscale x 8 x i16> %res
321}
322
323define <vscale x 4 x i32> @umax_i32_pos(<vscale x 4 x i32> %a) {
324; CHECK-LABEL: umax_i32_pos
325; CHECK: umax z0.s, z0.s, #27
326; CHECK-NEXT: ret
327  %elt = insertelement <vscale x 4 x i32> undef, i32 27, i32 0
328  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
329  %cmp = icmp ugt <vscale x 4 x i32> %a, %splat
330  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %splat
331  ret <vscale x 4 x i32> %res
332}
333
334define <vscale x 4 x i32> @umax_i32_out_of_range(<vscale x 4 x i32> %a) {
335; CHECK-LABEL: umax_i32_out_of_range:
336; CHECK:    mov w8, #257
337; CHECK-NEXT:    mov z1.s, w8
338; CHECK-NEXT:    ptrue p0.s
339; CHECK-NEXT:    umax z0.s, p0/m, z0.s, z1.s
340; CHECK-NEXT:    ret
341  %elt = insertelement <vscale x 4 x i32> undef, i32 257, i32 0
342  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
343  %cmp = icmp ugt <vscale x 4 x i32> %a, %splat
344  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %splat
345  ret <vscale x 4 x i32> %res
346}
347
348define <vscale x 2 x i64> @umax_i64_pos(<vscale x 2 x i64> %a) {
349; CHECK-LABEL: umax_i64_pos
350; CHECK: umax z0.d, z0.d, #27
351; CHECK-NEXT: ret
352  %elt = insertelement <vscale x 2 x i64> undef, i64 27, i32 0
353  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
354  %cmp = icmp ugt <vscale x 2 x i64> %a, %splat
355  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %splat
356  ret <vscale x 2 x i64> %res
357}
358
359define <vscale x 2 x i64> @umax_i64_out_of_range(<vscale x 2 x i64> %a) {
360; CHECK-LABEL: umax_i64_out_of_range:
361; CHECK:    mov w8, #65535
362; CHECK-NEXT:    mov z1.d, x8
363; CHECK-NEXT:    ptrue p0.d
364; CHECK-NEXT:    umax z0.d, p0/m, z0.d, z1.d
365; CHECK-NEXT:    ret
366  %elt = insertelement <vscale x 2 x i64> undef, i64 65535, i32 0
367  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
368  %cmp = icmp ugt <vscale x 2 x i64> %a, %splat
369  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %splat
370  ret <vscale x 2 x i64> %res
371}
372
373;
374; UMIN
375;
376define <vscale x 16 x i8> @umin_i8_pos(<vscale x 16 x i8> %a) {
377; CHECK-LABEL: umin_i8_pos
378; CHECK: umin z0.b, z0.b, #27
379; CHECK-NEXT: ret
380  %elt = insertelement <vscale x 16 x i8> undef, i8 27, i32 0
381  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
382  %cmp = icmp ult <vscale x 16 x i8> %a, %splat
383  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %splat
384  ret <vscale x 16 x i8> %res
385}
386
387define <vscale x 16 x i8> @umin_i8_large(<vscale x 16 x i8> %a) {
388; CHECK-LABEL: umin_i8_large
389; CHECK: umin z0.b, z0.b, #129
390; CHECK-NEXT: ret
391  %elt = insertelement <vscale x 16 x i8> undef, i8 129, i32 0
392  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
393  %cmp = icmp ult <vscale x 16 x i8> %a, %splat
394  %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %splat
395  ret <vscale x 16 x i8> %res
396}
397
398define <vscale x 8 x i16> @umin_i16_pos(<vscale x 8 x i16> %a) {
399; CHECK-LABEL: umin_i16_pos
400; CHECK: umin z0.h, z0.h, #27
401; CHECK-NEXT: ret
402  %elt = insertelement <vscale x 8 x i16> undef, i16 27, i32 0
403  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
404  %cmp = icmp ult <vscale x 8 x i16> %a, %splat
405  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %splat
406  ret <vscale x 8 x i16> %res
407}
408
409define <vscale x 8 x i16> @umin_i16_out_of_range(<vscale x 8 x i16> %a) {
410; CHECK-LABEL: umin_i16_out_of_range:
411; CHECK:    mov w8, #257
412; CHECK-NEXT:    mov z1.h, w8
413; CHECK-NEXT:    ptrue p0.h
414; CHECK-NEXT:    umin z0.h, p0/m, z0.h, z1.h
415; CHECK-NEXT:    ret
416  %elt = insertelement <vscale x 8 x i16> undef, i16 257, i32 0
417  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
418  %cmp = icmp ult <vscale x 8 x i16> %a, %splat
419  %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %splat
420  ret <vscale x 8 x i16> %res
421}
422
423define <vscale x 4 x i32> @umin_i32_pos(<vscale x 4 x i32> %a) {
424; CHECK-LABEL: umin_i32_pos
425; CHECK: umin z0.s, z0.s, #27
426; CHECK-NEXT: ret
427  %elt = insertelement <vscale x 4 x i32> undef, i32 27, i32 0
428  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
429  %cmp = icmp ult <vscale x 4 x i32> %a, %splat
430  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %splat
431  ret <vscale x 4 x i32> %res
432}
433
434define <vscale x 4 x i32> @umin_i32_out_of_range(<vscale x 4 x i32> %a) {
435; CHECK-LABEL: umin_i32_out_of_range:
436; CHECK:    mov w8, #257
437; CHECK-NEXT:    mov z1.s, w8
438; CHECK-NEXT:    ptrue p0.s
439; CHECK-NEXT:    umin z0.s, p0/m, z0.s, z1.s
440; CHECK-NEXT:    ret
441  %elt = insertelement <vscale x 4 x i32> undef, i32 257, i32 0
442  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
443  %cmp = icmp ult <vscale x 4 x i32> %a, %splat
444  %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %splat
445  ret <vscale x 4 x i32> %res
446}
447
448define <vscale x 2 x i64> @umin_i64_pos(<vscale x 2 x i64> %a) {
449; CHECK-LABEL: umin_i64_pos
450; CHECK: umin z0.d, z0.d, #27
451; CHECK-NEXT: ret
452  %elt = insertelement <vscale x 2 x i64> undef, i64 27, i32 0
453  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
454  %cmp = icmp ult <vscale x 2 x i64> %a, %splat
455  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %splat
456  ret <vscale x 2 x i64> %res
457}
458
459define <vscale x 2 x i64> @umin_i64_out_of_range(<vscale x 2 x i64> %a) {
460; CHECK-LABEL: umin_i64_out_of_range:
461; CHECK:    mov w8, #65535
462; CHECK-NEXT:    mov z1.d, x8
463; CHECK-NEXT:    ptrue p0.d
464; CHECK-NEXT:    umin z0.d, p0/m, z0.d, z1.d
465; CHECK-NEXT:    ret
466  %elt = insertelement <vscale x 2 x i64> undef, i64 65535, i32 0
467  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
468  %cmp = icmp ult <vscale x 2 x i64> %a, %splat
469  %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %splat
470  ret <vscale x 2 x i64> %res
471}
472
473;
474; MUL
475;
476define <vscale x 16 x i8> @mul_i8_neg(<vscale x 16 x i8> %a) {
477; CHECK-LABEL: mul_i8_neg
478; CHECK: mul z0.b, z0.b, #-17
479; CHECK-NEXT: ret
480  %elt = insertelement <vscale x 16 x i8> undef, i8 -17, i32 0
481  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
482  %res = mul <vscale x 16 x i8> %a, %splat
483  ret <vscale x 16 x i8> %res
484}
485
486define <vscale x 16 x i8> @mul_i8_pos(<vscale x 16 x i8> %a) {
487; CHECK-LABEL: mul_i8_pos
488; CHECK: mul z0.b, z0.b, #105
489; CHECK-NEXT: ret
490  %elt = insertelement <vscale x 16 x i8> undef, i8 105, i32 0
491  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
492  %res = mul <vscale x 16 x i8> %a, %splat
493  ret <vscale x 16 x i8> %res
494}
495
496define <vscale x 8 x i16> @mul_i16_neg(<vscale x 8 x i16> %a) {
497; CHECK-LABEL: mul_i16_neg
498; CHECK: mul z0.h, z0.h, #-17
499; CHECK-NEXT: ret
500  %elt = insertelement <vscale x 8 x i16> undef, i16 -17, i32 0
501  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
502  %res = mul <vscale x 8 x i16> %a, %splat
503  ret <vscale x 8 x i16> %res
504}
505
506define <vscale x 8 x i16> @mul_i16_pos(<vscale x 8 x i16> %a) {
507; CHECK-LABEL: mul_i16_pos
508; CHECK: mul z0.h, z0.h, #105
509; CHECK-NEXT: ret
510  %elt = insertelement <vscale x 8 x i16> undef, i16 105, i32 0
511  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
512  %res = mul <vscale x 8 x i16> %a, %splat
513  ret <vscale x 8 x i16> %res
514}
515
516define <vscale x 4 x i32> @mul_i32_neg(<vscale x 4 x i32> %a) {
517; CHECK-LABEL: mul_i32_neg
518; CHECK: mul z0.s, z0.s, #-17
519; CHECK-NEXT: ret
520  %elt = insertelement <vscale x 4 x i32> undef, i32 -17, i32 0
521  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
522  %res = mul <vscale x 4 x i32> %a, %splat
523  ret <vscale x 4 x i32> %res
524}
525
526define <vscale x 4 x i32> @mul_i32_pos(<vscale x 4 x i32> %a) {
527; CHECK-LABEL: mul_i32_pos
528; CHECK: mul z0.s, z0.s, #105
529; CHECK-NEXT: ret
530  %elt = insertelement <vscale x 4 x i32> undef, i32 105, i32 0
531  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
532  %res = mul <vscale x 4 x i32> %a, %splat
533  ret <vscale x 4 x i32> %res
534}
535
536define <vscale x 2 x i64> @mul_i64_neg(<vscale x 2 x i64> %a) {
537; CHECK-LABEL: mul_i64_neg
538; CHECK: mul z0.d, z0.d, #-17
539; CHECK-NEXT: ret
540  %elt = insertelement <vscale x 2 x i64> undef, i64 -17, i32 0
541  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
542  %res = mul <vscale x 2 x i64> %a, %splat
543  ret <vscale x 2 x i64> %res
544}
545
546define <vscale x 2 x i64> @mul_i64_pos(<vscale x 2 x i64> %a) {
547; CHECK-LABEL: mul_i64_pos
548; CHECK: mul z0.d, z0.d, #105
549; CHECK-NEXT: ret
550  %elt = insertelement <vscale x 2 x i64> undef, i64 105, i32 0
551  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
552  %res = mul <vscale x 2 x i64> %a, %splat
553  ret <vscale x 2 x i64> %res
554}
555
556define <vscale x 8 x i16> @mul_i16_range(<vscale x 8 x i16> %a) {
557; CHECK-LABEL: mul_i16_range
558; CHECK: mov w[[W:[0-9]+]], #255
559; CHECK-NEXT: mov z1.h, w[[W]]
560; CHECK: ptrue p0.h
561; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h
562  %elt = insertelement <vscale x 8 x i16> undef, i16 255, i32 0
563  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
564  %res = mul <vscale x 8 x i16> %a, %splat
565  ret <vscale x 8 x i16> %res
566}
567
568define <vscale x 4 x i32> @mul_i32_range(<vscale x 4 x i32> %a) {
569; CHECK-LABEL: mul_i32_range
570; CHECK: mov w[[W:[0-9]+]], #255
571; CHECK-NEXT: mov z1.s, w[[W]]
572; CHECK: ptrue p0.s
573; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s
574  %elt = insertelement <vscale x 4 x i32> undef, i32 255, i32 0
575  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
576  %res = mul <vscale x 4 x i32> %a, %splat
577  ret <vscale x 4 x i32> %res
578}
579
580define <vscale x 2 x i64> @mul_i64_range(<vscale x 2 x i64> %a) {
581; CHECK-LABEL: mul_i64_range
582; CHECK: mov w[[W:[0-9]+]], #255
583; CHECK-NEXT: mov z1.d, x[[W]]
584; CHECK: ptrue p0.d
585; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
586  %elt = insertelement <vscale x 2 x i64> undef, i64 255, i32 0
587  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
588  %res = mul <vscale x 2 x i64> %a, %splat
589  ret <vscale x 2 x i64> %res
590}
591
592; ASR
593
594define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i8> %a){
595; CHECK-LABEL: @asr_i8
596; CHECK-DAG: asr z0.b, z0.b, #8
597; CHECK-NEXT: ret
598  %elt = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
599  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
600  %lshr = ashr <vscale x 16 x i8> %a, %splat
601  ret <vscale x 16 x i8> %lshr
602}
603
604define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i16> %a){
605; CHECK-LABEL: @asr_i16
606; CHECK-DAG: asr z0.h, z0.h, #16
607; CHECK-NEXT: ret
608  %elt = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
609  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
610  %ashr = ashr <vscale x 8 x i16> %a, %splat
611  ret <vscale x 8 x i16> %ashr
612}
613
614define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i32> %a){
615; CHECK-LABEL: @asr_i32
616; CHECK-DAG: asr z0.s, z0.s, #32
617; CHECK-NEXT: ret
618  %elt = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
619  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
620  %ashr = ashr <vscale x 4 x i32> %a, %splat
621  ret <vscale x 4 x i32> %ashr
622}
623
624define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i64> %a){
625; CHECK-LABEL: @asr_i64
626; CHECK-DAG: asr z0.d, z0.d, #64
627; CHECK-NEXT: ret
628  %elt = insertelement <vscale x 2 x i64> undef, i64 64, i32 0
629  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
630  %ashr = ashr <vscale x 2 x i64> %a, %splat
631  ret <vscale x 2 x i64> %ashr
632}
633
634; LSL
635
636define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i8> %a){
637; CHECK-LABEL: @lsl_i8
638; CHECK-DAG: lsl z0.b, z0.b, #7
639; CHECK-NEXT: ret
640  %elt = insertelement <vscale x 16 x i8> undef, i8 7, i32 0
641  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
642  %shl = shl <vscale x 16 x i8> %a, %splat
643  ret <vscale x 16 x i8> %shl
644}
645
646define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i16> %a){
647; CHECK-LABEL: @lsl_i16
648; CHECK-DAG: lsl z0.h, z0.h, #15
649; CHECK-NEXT: ret
650  %elt = insertelement <vscale x 8 x i16> undef, i16 15, i32 0
651  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
652  %shl = shl <vscale x 8 x i16> %a, %splat
653  ret <vscale x 8 x i16> %shl
654}
655
656define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i32> %a){
657; CHECK-LABEL: @lsl_i32
658; CHECK-DAG: lsl z0.s, z0.s, #31
659; CHECK-NEXT: ret
660  %elt = insertelement <vscale x 4 x i32> undef, i32 31, i32 0
661  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
662  %shl = shl <vscale x 4 x i32> %a, %splat
663  ret <vscale x 4 x i32> %shl
664}
665
666define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i64> %a){
667; CHECK-LABEL: @lsl_i64
668; CHECK-DAG: lsl z0.d, z0.d, #63
669; CHECK-NEXT: ret
670  %elt = insertelement <vscale x 2 x i64> undef, i64 63, i32 0
671  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
672  %shl = shl <vscale x 2 x i64> %a, %splat
673  ret <vscale x 2 x i64> %shl
674}
675
676; LSR
677
678define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i8> %a){
679; CHECK-LABEL: @lsr_i8
680; CHECK-DAG: lsr z0.b, z0.b, #8
681; CHECK-NEXT: ret
682  %elt = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
683  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
684  %lshr = lshr <vscale x 16 x i8> %a, %splat
685  ret <vscale x 16 x i8> %lshr
686}
687
688define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i16> %a){
689; CHECK-LABEL: @lsr_i16
690; CHECK-DAG: lsr z0.h, z0.h, #16
691; CHECK-NEXT: ret
692  %elt = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
693  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
694  %lshr = lshr <vscale x 8 x i16> %a, %splat
695  ret <vscale x 8 x i16> %lshr
696}
697
698define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i32> %a){
699; CHECK-LABEL: @lsr_i32
700; CHECK-DAG: lsr z0.s, z0.s, #32
701; CHECK-NEXT: ret
702  %elt = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
703  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
704  %lshr = lshr <vscale x 4 x i32> %a, %splat
705  ret <vscale x 4 x i32> %lshr
706}
707
708define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i64> %a){
709; CHECK-LABEL: @lsr_i64
710; CHECK-DAG: lsr z0.d, z0.d, #64
711; CHECK-NEXT: ret
712  %elt = insertelement <vscale x 2 x i64> undef, i64 64, i32 0
713  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
714  %lshr = lshr <vscale x 2 x i64> %a, %splat
715  ret <vscale x 2 x i64> %lshr
716}
717