1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s 2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 3 4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 5; WARN-NOT: warning 6 7; 8; SVE Logical Vector Immediate Unpredicated CodeGen 9; 10 11; ORR 12define <vscale x 16 x i8> @orr_i8(<vscale x 16 x i8> %a) { 13; CHECK-LABEL: orr_i8: 14; CHECK: orr z0.b, z0.b, #0xf 15; CHECK-NEXT: ret 16 %elt = insertelement <vscale x 16 x i8> undef, i8 15, i32 0 17 %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 18 %res = or <vscale x 16 x i8> %a, %splat 19 ret <vscale x 16 x i8> %res 20} 21 22define <vscale x 8 x i16> @orr_i16(<vscale x 8 x i16> %a) { 23; CHECK-LABEL: orr_i16: 24; CHECK: orr z0.h, z0.h, #0xfc07 25; CHECK-NEXT: ret 26 %elt = insertelement <vscale x 8 x i16> undef, i16 64519, i32 0 27 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 28 %res = or <vscale x 8 x i16> %a, %splat 29 ret <vscale x 8 x i16> %res 30} 31 32define <vscale x 4 x i32> @orr_i32(<vscale x 4 x i32> %a) { 33; CHECK-LABEL: orr_i32: 34; CHECK: orr z0.s, z0.s, #0xffff00 35; CHECK-NEXT: ret 36 %elt = insertelement <vscale x 4 x i32> undef, i32 16776960, i32 0 37 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 38 %res = or <vscale x 4 x i32> %a, %splat 39 ret <vscale x 4 x i32> %res 40} 41 42define <vscale x 2 x i64> @orr_i64(<vscale x 2 x i64> %a) { 43; CHECK-LABEL: orr_i64: 44; CHECK: orr z0.d, z0.d, #0xfffc000000000000 45; CHECK-NEXT: ret 46 %elt = insertelement <vscale x 2 x i64> undef, i64 18445618173802708992, i32 0 47 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 48 %res = or <vscale x 2 x i64> %a, %splat 49 ret <vscale x 2 x i64> %res 50} 51 52; EOR 53define <vscale x 16 x i8> @eor_i8(<vscale x 16 x i8> %a) { 54; CHECK-LABEL: eor_i8: 55; CHECK: eor z0.b, z0.b, #0xf 56; CHECK-NEXT: ret 57 %elt = insertelement <vscale x 16 x i8> undef, i8 15, i32 0 58 %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 59 %res = xor <vscale x 16 x i8> %a, %splat 60 ret <vscale x 16 x i8> %res 61} 62 63define <vscale x 8 x i16> @eor_i16(<vscale x 8 x i16> %a) { 64; CHECK-LABEL: eor_i16: 65; CHECK: eor z0.h, z0.h, #0xfc07 66; CHECK-NEXT: ret 67 %elt = insertelement <vscale x 8 x i16> undef, i16 64519, i32 0 68 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 69 %res = xor <vscale x 8 x i16> %a, %splat 70 ret <vscale x 8 x i16> %res 71} 72 73define <vscale x 4 x i32> @eor_i32(<vscale x 4 x i32> %a) { 74; CHECK-LABEL: eor_i32: 75; CHECK: eor z0.s, z0.s, #0xffff00 76; CHECK-NEXT: ret 77 %elt = insertelement <vscale x 4 x i32> undef, i32 16776960, i32 0 78 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 79 %res = xor <vscale x 4 x i32> %a, %splat 80 ret <vscale x 4 x i32> %res 81} 82 83define <vscale x 2 x i64> @eor_i64(<vscale x 2 x i64> %a) { 84; CHECK-LABEL: eor_i64: 85; CHECK: eor z0.d, z0.d, #0xfffc000000000000 86; CHECK-NEXT: ret 87 %elt = insertelement <vscale x 2 x i64> undef, i64 18445618173802708992, i32 0 88 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 89 %res = xor <vscale x 2 x i64> %a, %splat 90 ret <vscale x 2 x i64> %res 91} 92 93; AND 94define <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> %a) { 95; CHECK-LABEL: and_i8: 96; CHECK: and z0.b, z0.b, #0xf 97; CHECK-NEXT: ret 98 %elt = insertelement <vscale x 16 x i8> undef, i8 15, i32 0 99 %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 100 %res = and <vscale x 16 x i8> %a, %splat 101 ret <vscale x 16 x i8> %res 102} 103 104define <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> %a) { 105; CHECK-LABEL: and_i16: 106; CHECK: and z0.h, z0.h, #0xfc07 107; CHECK-NEXT: ret 108 %elt = insertelement <vscale x 8 x i16> undef, i16 64519, i32 0 109 %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 110 %res = and <vscale x 8 x i16> %a, %splat 111 ret <vscale x 8 x i16> %res 112} 113 114define <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> %a) { 115; CHECK-LABEL: and_i32: 116; CHECK: and z0.s, z0.s, #0xffff00 117; CHECK-NEXT: ret 118 %elt = insertelement <vscale x 4 x i32> undef, i32 16776960, i32 0 119 %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 120 %res = and <vscale x 4 x i32> %a, %splat 121 ret <vscale x 4 x i32> %res 122} 123 124define <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> %a) { 125; CHECK-LABEL: and_i64: 126; CHECK: and z0.d, z0.d, #0xfffc000000000000 127; CHECK-NEXT: ret 128 %elt = insertelement <vscale x 2 x i64> undef, i64 18445618173802708992, i32 0 129 %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 130 %res = and <vscale x 2 x i64> %a, %splat 131 ret <vscale x 2 x i64> %res 132} 133