1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s 2>%t | FileCheck %s 2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 3 4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 5; WARN-NOT: warning 6 7; 8; ADRB 9; 10 11define <vscale x 4 x i32> @adrb_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { 12; CHECK-LABEL: adrb_i32: 13; CHECK: adr z0.s, [z0.s, z1.s] 14; CHECK-NEXT: ret 15 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %a, 16 <vscale x 4 x i32> %b) 17 ret <vscale x 4 x i32> %out 18} 19 20define <vscale x 2 x i64> @adrb_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { 21; CHECK-LABEL: adrb_i64: 22; CHECK: adr z0.d, [z0.d, z1.d] 23; CHECK-NEXT: ret 24 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %a, 25 <vscale x 2 x i64> %b) 26 ret <vscale x 2 x i64> %out 27} 28 29; 30; ADRH 31; 32 33define <vscale x 4 x i32> @adrh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { 34; CHECK-LABEL: adrh_i32: 35; CHECK: adr z0.s, [z0.s, z1.s, lsl #1] 36; CHECK-NEXT: ret 37 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %a, 38 <vscale x 4 x i32> %b) 39 ret <vscale x 4 x i32> %out 40} 41 42define <vscale x 2 x i64> @adrh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { 43; CHECK-LABEL: adrh_i64: 44; CHECK: adr z0.d, [z0.d, z1.d, lsl #1] 45; CHECK-NEXT: ret 46 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %a, 47 <vscale x 2 x i64> %b) 48 ret <vscale x 2 x i64> %out 49} 50 51; 52; ADRW 53; 54 55define <vscale x 4 x i32> @adrw_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { 56; CHECK-LABEL: adrw_i32: 57; CHECK: adr z0.s, [z0.s, z1.s, lsl #2] 58; CHECK-NEXT: ret 59 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %a, 60 <vscale x 4 x i32> %b) 61 ret <vscale x 4 x i32> %out 62} 63 64define <vscale x 2 x i64> @adrw_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { 65; CHECK-LABEL: adrw_i64: 66; CHECK: adr z0.d, [z0.d, z1.d, lsl #2] 67; CHECK-NEXT: ret 68 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %a, 69 <vscale x 2 x i64> %b) 70 ret <vscale x 2 x i64> %out 71} 72 73; 74; ADRD 75; 76 77define <vscale x 4 x i32> @adrd_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { 78; CHECK-LABEL: adrd_i32: 79; CHECK: adr z0.s, [z0.s, z1.s, lsl #3] 80; CHECK-NEXT: ret 81 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %a, 82 <vscale x 4 x i32> %b) 83 ret <vscale x 4 x i32> %out 84} 85 86define <vscale x 2 x i64> @adrd_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { 87; CHECK-LABEL: adrd_i64: 88; CHECK: adr z0.d, [z0.d, z1.d, lsl #3] 89; CHECK-NEXT: ret 90 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %a, 91 <vscale x 2 x i64> %b) 92 ret <vscale x 2 x i64> %out 93} 94 95declare <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) 96declare <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) 97 98declare <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) 99declare <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) 100 101declare <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) 102declare <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) 103 104declare <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) 105declare <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) 106