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1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
3
4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
5; WARN-NOT: warning
6
7;
8; LD1B, LD1W, LD1H, LD1D: base + 64-bit unscaled offset
9;   e.g. ld1h { z0.d }, p0/z, [x0, z0.d]
10;
11
12define <vscale x 2 x i64> @gld1b_d(<vscale x 2 x i1> %pg, i8* %base, <vscale x 2 x i64> %b) {
13; CHECK-LABEL: gld1b_d:
14; CHECK: ld1b { z0.d }, p0/z, [x0, z0.d]
15; CHECK-NEXT: ret
16  %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1> %pg,
17                                                                     i8* %base,
18                                                                     <vscale x 2 x i64> %b)
19  %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
20  ret <vscale x 2 x i64> %res
21}
22
23define <vscale x 2 x i64> @gld1h_d(<vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i64> %b) {
24; CHECK-LABEL: gld1h_d:
25; CHECK: ld1h { z0.d }, p0/z, [x0, z0.d]
26; CHECK-NEXT: ret
27  %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1> %pg,
28                                                                       i16* %base,
29                                                                       <vscale x 2 x i64> %b)
30  %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
31  ret <vscale x 2 x i64> %res
32}
33
34define <vscale x 2 x i64> @gld1w_d(<vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i64> %offsets) {
35; CHECK-LABEL: gld1w_d:
36; CHECK: ld1w { z0.d }, p0/z, [x0, z0.d]
37; CHECK-NEXT: ret
38  %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32(<vscale x 2 x i1> %pg,
39                                                                       i32* %base,
40                                                                       <vscale x 2 x i64> %offsets)
41  %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
42  ret <vscale x 2 x i64> %res
43}
44
45define <vscale x 2 x i64> @gld1d_d(<vscale x 2 x i1> %pg, i64* %base, <vscale x 2 x i64> %b) {
46; CHECK-LABEL: gld1d_d:
47; CHECK: ld1d { z0.d }, p0/z, [x0, z0.d]
48; CHECK-NEXT: ret
49  %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.nxv2i64(<vscale x 2 x i1> %pg,
50                                                                       i64* %base,
51                                                                       <vscale x 2 x i64> %b)
52  ret <vscale x 2 x i64> %load
53}
54
55define <vscale x 2 x double> @gld1d_d_double(<vscale x 2 x i1> %pg, double* %base, <vscale x 2 x i64> %b) {
56; CHECK-LABEL: gld1d_d_double:
57; CHECK: ld1d { z0.d }, p0/z, [x0, z0.d]
58; CHECK-NEXT: ret
59  %load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.nxv2f64(<vscale x 2 x i1> %pg,
60                                                                       double* %base,
61                                                                       <vscale x 2 x i64> %b)
62  ret <vscale x 2 x double> %load
63}
64
65;
66; LD1SB, LD1SW, LD1SH: base + 64-bit unscaled offset
67;   e.g. ld1sh { z0.d }, p0/z, [x0, z0.d]
68;
69
70define <vscale x 2 x i64> @gld1sb_d(<vscale x 2 x i1> %pg, i8* %base, <vscale x 2 x i64> %b) {
71; CHECK-LABEL: gld1sb_d:
72; CHECK: ld1sb { z0.d }, p0/z, [x0, z0.d]
73; CHECK-NEXT: ret
74  %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1> %pg,
75                                                                     i8* %base,
76                                                                     <vscale x 2 x i64> %b)
77  %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>
78  ret <vscale x 2 x i64> %res
79}
80
81define <vscale x 2 x i64> @gld1sh_d(<vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i64> %b) {
82; CHECK-LABEL: gld1sh_d:
83; CHECK: ld1sh { z0.d }, p0/z, [x0, z0.d]
84; CHECK-NEXT: ret
85  %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1> %pg,
86                                                                       i16* %base,
87                                                                       <vscale x 2 x i64> %b)
88  %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>
89  ret <vscale x 2 x i64> %res
90}
91
92define <vscale x 2 x i64> @gld1sw_d(<vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i64> %offsets) {
93; CHECK-LABEL: gld1sw_d:
94; CHECK: ld1sw { z0.d }, p0/z, [x0, z0.d]
95; CHECK-NEXT: ret
96  %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32(<vscale x 2 x i1> %pg,
97                                                                       i32* %base,
98                                                                       <vscale x 2 x i64> %offsets)
99  %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
100  ret <vscale x 2 x i64> %res
101}
102
103declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1>, i8*, <vscale x 2 x i64>)
104declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1>, i16*, <vscale x 2 x i64>)
105declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32(<vscale x 2 x i1>, i32*, <vscale x 2 x i64>)
106declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.nxv2i64(<vscale x 2 x i1>, i64*, <vscale x 2 x i64>)
107declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.nxv2f64(<vscale x 2 x i1>, double*, <vscale x 2 x i64>)
108