1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s 2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 3 4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 5; WARN-NOT: warning 6 7; 8; LD1B, LD1W, LD1H, LD1D: vector base + scalar offset (index) 9; e.g. ld1b { z0.d }, p0/z, [x0, z0.d] 10; 11 12; LD1B 13define <vscale x 4 x i32> @gld1b_s_scalar_offset(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) { 14; CHECK-LABEL: gld1b_s_scalar_offset: 15; CHECK: ld1b { z0.s }, p0/z, [x0, z0.s, uxtw] 16; CHECK-NEXT: ret 17 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32(<vscale x 4 x i1> %pg, 18 <vscale x 4 x i32> %base, 19 i64 %offset) 20 %res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32> 21 ret <vscale x 4 x i32> %res 22} 23 24define <vscale x 2 x i64> @gld1b_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 25; CHECK-LABEL: gld1b_d_scalar_offset: 26; CHECK: ld1b { z0.d }, p0/z, [x0, z0.d] 27; CHECK-NEXT: ret 28 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i1> %pg, 29 <vscale x 2 x i64> %base, 30 i64 %offset) 31 %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64> 32 ret <vscale x 2 x i64> %res 33} 34 35; LD1H 36define <vscale x 4 x i32> @gld1h_s_scalar_offset(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) { 37; CHECK-LABEL: gld1h_s_scalar_offset: 38; CHECK: ld1h { z0.s }, p0/z, [x0, z0.s, uxtw] 39; CHECK-NEXT: ret 40 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %pg, 41 <vscale x 4 x i32> %base, 42 i64 %offset) 43 %res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32> 44 ret <vscale x 4 x i32> %res 45} 46 47define <vscale x 2 x i64> @gld1h_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 48; CHECK-LABEL: gld1h_d_scalar_offset: 49; CHECK: ld1h { z0.d }, p0/z, [x0, z0.d] 50; CHECK-NEXT: ret 51 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %pg, 52 <vscale x 2 x i64> %base, 53 i64 %offset) 54 %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64> 55 ret <vscale x 2 x i64> %res 56} 57 58; LD1W 59define <vscale x 4 x i32> @gld1w_s_scalar_offset(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) { 60; CHECK-LABEL: gld1w_s_scalar_offset: 61; CHECK: ld1w { z0.s }, p0/z, [x0, z0.s, uxtw] 62; CHECK-NEXT: ret 63 %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32(<vscale x 4 x i1> %pg, 64 <vscale x 4 x i32> %base, 65 i64 %offset) 66 ret <vscale x 4 x i32> %load 67} 68 69define <vscale x 2 x i64> @gld1w_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 70; CHECK-LABEL: gld1w_d_scalar_offset: 71; CHECK: ld1w { z0.d }, p0/z, [x0, z0.d] 72; CHECK-NEXT: ret 73 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %pg, 74 <vscale x 2 x i64> %base, 75 i64 %offset) 76 %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64> 77 ret <vscale x 2 x i64> %res 78} 79 80define <vscale x 4 x float> @gld1w_s_scalar_offset_float(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) { 81; CHECK-LABEL: gld1w_s_scalar_offset_float: 82; CHECK: ld1w { z0.s }, p0/z, [x0, z0.s, uxtw] 83; CHECK-NEXT: ret 84 %load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4f32.nxv4i32(<vscale x 4 x i1> %pg, 85 <vscale x 4 x i32> %base, 86 i64 %offset) 87 ret <vscale x 4 x float> %load 88} 89 90; LD1D 91define <vscale x 2 x i64> @gld1d_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 92; CHECK-LABEL: gld1d_d_scalar_offset: 93; CHECK: ld1d { z0.d }, p0/z, [x0, z0.d] 94; CHECK-NEXT: ret 95 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i1> %pg, 96 <vscale x 2 x i64> %base, 97 i64 %offset) 98 ret <vscale x 2 x i64> %load 99} 100 101define <vscale x 2 x double> @gld1d_d_scalar_offset_double(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 102; CHECK-LABEL: gld1d_d_scalar_offset_double: 103; CHECK: ld1d { z0.d }, p0/z, [x0, z0.d] 104; CHECK-NEXT: ret 105 %load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 2 x i1> %pg, 106 <vscale x 2 x i64> %base, 107 i64 %offset) 108 ret <vscale x 2 x double> %load 109} 110 111; LD1SB, LD1SW, LD1SH: vector base + scalar offset (index) 112; e.g. ld1b { z0.d }, p0/z, [x0, z0.d] 113; 114 115; LD1SB 116define <vscale x 4 x i32> @gld1sb_s_scalar_offset(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) { 117; CHECK-LABEL: gld1sb_s_scalar_offset: 118; CHECK: ld1sb { z0.s }, p0/z, [x0, z0.s, uxtw] 119; CHECK-NEXT: ret 120 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32(<vscale x 4 x i1> %pg, 121 <vscale x 4 x i32> %base, 122 i64 %offset) 123 %res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32> 124 ret <vscale x 4 x i32> %res 125} 126 127define <vscale x 2 x i64> @gld1sb_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 128; CHECK-LABEL: gld1sb_d_scalar_offset: 129; CHECK: ld1sb { z0.d }, p0/z, [x0, z0.d] 130; CHECK-NEXT: ret 131 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i1> %pg, 132 <vscale x 2 x i64> %base, 133 i64 %offset) 134 %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64> 135 ret <vscale x 2 x i64> %res 136} 137 138; LD1SH 139define <vscale x 4 x i32> @gld1sh_s_scalar_offset(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) { 140; CHECK-LABEL: gld1sh_s_scalar_offset: 141; CHECK: ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw] 142; CHECK-NEXT: ret 143 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %pg, 144 <vscale x 4 x i32> %base, 145 i64 %offset) 146 %res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32> 147 ret <vscale x 4 x i32> %res 148} 149 150define <vscale x 2 x i64> @gld1sh_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 151; CHECK-LABEL: gld1sh_d_scalar_offset: 152; CHECK: ld1sh { z0.d }, p0/z, [x0, z0.d] 153; CHECK-NEXT: ret 154 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %pg, 155 <vscale x 2 x i64> %base, 156 i64 %offset) 157 %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64> 158 ret <vscale x 2 x i64> %res 159} 160 161; LD1SW 162define <vscale x 2 x i64> @gld1sw_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 163; CHECK-LABEL: gld1sw_d_scalar_offset: 164; CHECK: ld1sw { z0.d }, p0/z, [x0, z0.d] 165; CHECK-NEXT: ret 166 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %pg, 167 <vscale x 2 x i64> %base, 168 i64 %offset) 169 %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64> 170 ret <vscale x 2 x i64> %res 171} 172 173; LD1B/LD1SB 174declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) 175declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) 176 177; LD1H/LD1SH 178declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) 179declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) 180 181; LD1W/LD1SW 182declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) 183declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) 184 185declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4f32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) 186 187; LD1D 188declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) 189 190declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) 191