1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s 2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 3 4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 5; WARN-NOT: warning 6 7; 8; RBIT 9; 10 11define <vscale x 16 x i8> @rbit_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) { 12; CHECK-LABEL: rbit_i8: 13; CHECK: rbit z0.b, p0/m, z1.b 14; CHECK-NEXT: ret 15 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> %a, 16 <vscale x 16 x i1> %pg, 17 <vscale x 16 x i8> %b) 18 ret <vscale x 16 x i8> %out 19} 20 21define <vscale x 8 x i16> @rbit_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) { 22; CHECK-LABEL: rbit_i16: 23; CHECK: rbit z0.h, p0/m, z1.h 24; CHECK-NEXT: ret 25 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> %a, 26 <vscale x 8 x i1> %pg, 27 <vscale x 8 x i16> %b) 28 ret <vscale x 8 x i16> %out 29} 30 31define <vscale x 4 x i32> @rbit_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) { 32; CHECK-LABEL: rbit_i32: 33; CHECK: rbit z0.s, p0/m, z1.s 34; CHECK-NEXT: ret 35 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> %a, 36 <vscale x 4 x i1> %pg, 37 <vscale x 4 x i32> %b) 38 ret <vscale x 4 x i32> %out 39} 40 41define <vscale x 2 x i64> @rbit_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) { 42; CHECK-LABEL: rbit_i64: 43; CHECK: rbit z0.d, p0/m, z1.d 44; CHECK-NEXT: ret 45 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> %a, 46 <vscale x 2 x i1> %pg, 47 <vscale x 2 x i64> %b) 48 ret <vscale x 2 x i64> %out 49} 50 51; 52; REVB 53; 54 55define <vscale x 8 x i16> @revb_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) { 56; CHECK-LABEL: revb_i16: 57; CHECK: revb z0.h, p0/m, z1.h 58; CHECK-NEXT: ret 59 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> %a, 60 <vscale x 8 x i1> %pg, 61 <vscale x 8 x i16> %b) 62 ret <vscale x 8 x i16> %out 63} 64 65define <vscale x 4 x i32> @revb_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) { 66; CHECK-LABEL: revb_i32: 67; CHECK: revb z0.s, p0/m, z1.s 68; CHECK-NEXT: ret 69 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> %a, 70 <vscale x 4 x i1> %pg, 71 <vscale x 4 x i32> %b) 72 ret <vscale x 4 x i32> %out 73} 74 75define <vscale x 2 x i64> @revb_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) { 76; CHECK-LABEL: revb_i64: 77; CHECK: revb z0.d, p0/m, z1.d 78; CHECK-NEXT: ret 79 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> %a, 80 <vscale x 2 x i1> %pg, 81 <vscale x 2 x i64> %b) 82 ret <vscale x 2 x i64> %out 83} 84 85; 86; REVB (bswap) 87; 88 89define <vscale x 8 x i16> @revb_i16_bswap(<vscale x 8 x i16> %a) { 90; CHECK-LABEL: revb_i16_bswap: 91; CHECK: ptrue [[PG:p[0-9]+]].h 92; CHECK-NEXT: revb z0.h, [[PG]]/m, z0.h 93; CHECK-NEXT: ret 94 %res = call <vscale x 8 x i16> @llvm.bswap.nxv8i16(<vscale x 8 x i16> %a) 95 ret <vscale x 8 x i16> %res 96} 97 98define <vscale x 4 x i32> @revb_i32_bswap(<vscale x 4 x i32> %a) { 99; CHECK-LABEL: revb_i32_bswap: 100; CHECK: ptrue [[PG:p[0-9]+]].s 101; CHECK-NEXT: revb z0.s, [[PG]]/m, z0.s 102; CHECK-NEXT: ret 103 %res = call <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32> %a) 104 ret <vscale x 4 x i32> %res 105} 106 107define <vscale x 2 x i64> @revb_i64_bswap(<vscale x 2 x i64> %a) { 108; CHECK-LABEL: revb_i64_bswap: 109; CHECK: ptrue [[PG:p[0-9]+]].d 110; CHECK-NEXT: revb z0.d, [[PG]]/m, z0.d 111; CHECK-NEXT: ret 112 %res = call <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64> %a) 113 ret <vscale x 2 x i64> %res 114} 115 116; 117; REVH 118; 119 120define <vscale x 4 x i32> @revh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) { 121; CHECK-LABEL: revh_i32: 122; CHECK: revh z0.s, p0/m, z1.s 123; CHECK-NEXT: ret 124 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %a, 125 <vscale x 4 x i1> %pg, 126 <vscale x 4 x i32> %b) 127 ret <vscale x 4 x i32> %out 128} 129 130define <vscale x 2 x i64> @revh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) { 131; CHECK-LABEL: revh_i64: 132; CHECK: revh z0.d, p0/m, z1.d 133; CHECK-NEXT: ret 134 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> %a, 135 <vscale x 2 x i1> %pg, 136 <vscale x 2 x i64> %b) 137 ret <vscale x 2 x i64> %out 138} 139 140; 141; REVW 142; 143 144define <vscale x 2 x i64> @revw_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) { 145; CHECK-LABEL: revw_i64: 146; CHECK: revw z0.d, p0/m, z1.d 147; CHECK-NEXT: ret 148 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %a, 149 <vscale x 2 x i1> %pg, 150 <vscale x 2 x i64> %b) 151 ret <vscale x 2 x i64> %out 152} 153 154declare <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) 155declare <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) 156declare <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) 157declare <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) 158 159declare <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) 160declare <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) 161declare <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) 162 163declare <vscale x 8 x i16> @llvm.bswap.nxv8i16(<vscale x 8 x i16>) 164declare <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32>) 165declare <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64>) 166 167declare <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) 168declare <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) 169 170declare <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) 171