1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s 2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 3 4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 5; WARN-NOT: warning 6 7; 8; ST1H, ST1W, ST1D: base + 32-bit scaled offset, sign (sxtw) or zero 9; (uxtw) extended to 64 bits. 10; e.g. st1h { z0.d }, p0, [x0, z1.d, uxtw #1] 11; 12 13; ST1H 14define void @sst1h_s_uxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, i16* %base, <vscale x 4 x i32> %indices) { 15; CHECK-LABEL: sst1h_s_uxtw: 16; CHECK: st1h { z0.s }, p0, [x0, z1.s, uxtw #1] 17; CHECK-NEXT: ret 18 %data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16> 19 call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i16(<vscale x 4 x i16> %data_trunc, 20 <vscale x 4 x i1> %pg, 21 i16* %base, 22 <vscale x 4 x i32> %indices) 23 ret void 24} 25 26define void @sst1h_s_sxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, i16* %base, <vscale x 4 x i32> %indices) { 27; CHECK-LABEL: sst1h_s_sxtw: 28; CHECK: st1h { z0.s }, p0, [x0, z1.s, sxtw #1] 29; CHECK-NEXT: ret 30 %data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16> 31 call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i16(<vscale x 4 x i16> %data_trunc, 32 <vscale x 4 x i1> %pg, 33 i16* %base, 34 <vscale x 4 x i32> %indices) 35 ret void 36} 37 38define void @sst1h_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i32> %indices) { 39; CHECK-LABEL: sst1h_d_uxtw: 40; CHECK: st1h { z0.d }, p0, [x0, z1.d, uxtw #1] 41; CHECK-NEXT: ret 42 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16> 43 call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i16(<vscale x 2 x i16> %data_trunc, 44 <vscale x 2 x i1> %pg, 45 i16* %base, 46 <vscale x 2 x i32> %indices) 47 ret void 48} 49 50define void @sst1h_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i32> %indices) { 51; CHECK-LABEL: sst1h_d_sxtw: 52; CHECK: st1h { z0.d }, p0, [x0, z1.d, sxtw #1] 53; CHECK-NEXT: ret 54 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16> 55 call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i16(<vscale x 2 x i16> %data_trunc, 56 <vscale x 2 x i1> %pg, 57 i16* %base, 58 <vscale x 2 x i32> %indices) 59 ret void 60} 61 62; ST1W 63define void @sst1w_s_uxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, i32* %base, <vscale x 4 x i32> %indices) { 64; CHECK-LABEL: sst1w_s_uxtw: 65; CHECK: st1w { z0.s }, p0, [x0, z1.s, uxtw #2] 66; CHECK-NEXT: ret 67 call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i32(<vscale x 4 x i32> %data, 68 <vscale x 4 x i1> %pg, 69 i32* %base, 70 <vscale x 4 x i32> %indices) 71 ret void 72} 73 74define void @sst1w_s_sxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, i32* %base, <vscale x 4 x i32> %indices) { 75; CHECK-LABEL: sst1w_s_sxtw: 76; CHECK: st1w { z0.s }, p0, [x0, z1.s, sxtw #2] 77; CHECK-NEXT: ret 78 call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32(<vscale x 4 x i32> %data, 79 <vscale x 4 x i1> %pg, 80 i32* %base, 81 <vscale x 4 x i32> %indices) 82 ret void 83} 84 85define void @sst1w_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i32> %indices) { 86; CHECK-LABEL: sst1w_d_uxtw: 87; CHECK: st1w { z0.d }, p0, [x0, z1.d, uxtw #2] 88; CHECK-NEXT: ret 89 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32> 90 call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i32(<vscale x 2 x i32> %data_trunc, 91 <vscale x 2 x i1> %pg, 92 i32* %base, 93 <vscale x 2 x i32> %indices) 94 ret void 95} 96 97define void @sst1w_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i32> %indices) { 98; CHECK-LABEL: sst1w_d_sxtw: 99; CHECK: st1w { z0.d }, p0, [x0, z1.d, sxtw #2] 100; CHECK-NEXT: ret 101 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32> 102 call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i32(<vscale x 2 x i32> %data_trunc, 103 <vscale x 2 x i1> %pg, 104 i32* %base, 105 <vscale x 2 x i32> %indices) 106 ret void 107} 108 109define void @sst1w_s_uxtw_float(<vscale x 4 x float> %data, <vscale x 4 x i1> %pg, float* %base, <vscale x 4 x i32> %indices) { 110; CHECK-LABEL: sst1w_s_uxtw_float: 111; CHECK: st1w { z0.s }, p0, [x0, z1.s, uxtw #2] 112; CHECK-NEXT: ret 113 call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4f32(<vscale x 4 x float> %data, 114 <vscale x 4 x i1> %pg, 115 float* %base, 116 <vscale x 4 x i32> %indices) 117 ret void 118} 119 120define void @sst1w_s_sxtw_float(<vscale x 4 x float> %data, <vscale x 4 x i1> %pg, float* %base, <vscale x 4 x i32> %indices) { 121; CHECK-LABEL: sst1w_s_sxtw_float: 122; CHECK: st1w { z0.s }, p0, [x0, z1.s, sxtw #2] 123; CHECK-NEXT: ret 124 call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4f32(<vscale x 4 x float> %data, 125 <vscale x 4 x i1> %pg, 126 float* %base, 127 <vscale x 4 x i32> %indices) 128 ret void 129} 130 131; ST1D 132define void @sst1d_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i64* %base, <vscale x 2 x i32> %indices) { 133; CHECK-LABEL: sst1d_d_uxtw: 134; CHECK: st1d { z0.d }, p0, [x0, z1.d, uxtw #3] 135; CHECK-NEXT: ret 136 call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i64(<vscale x 2 x i64> %data, 137 <vscale x 2 x i1> %pg, 138 i64* %base, 139 <vscale x 2 x i32> %indices) 140 ret void 141} 142 143define void @sst1d_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i64* %base, <vscale x 2 x i32> %indices) { 144; CHECK-LABEL: sst1d_d_sxtw: 145; CHECK: st1d { z0.d }, p0, [x0, z1.d, sxtw #3] 146; CHECK-NEXT: ret 147 call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i64(<vscale x 2 x i64> %data, 148 <vscale x 2 x i1> %pg, 149 i64* %base, 150 <vscale x 2 x i32> %indices) 151 ret void 152} 153 154define void @sst1d_d_uxtw_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, double* %base, <vscale x 2 x i32> %indices) { 155; CHECK-LABEL: sst1d_d_uxtw_double: 156; CHECK: st1d { z0.d }, p0, [x0, z1.d, uxtw #3] 157; CHECK-NEXT: ret 158 call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2f64(<vscale x 2 x double> %data, 159 <vscale x 2 x i1> %pg, 160 double* %base, 161 <vscale x 2 x i32> %indices) 162 ret void 163} 164 165define void @sst1d_d_sxtw_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, double* %base, <vscale x 2 x i32> %indices) { 166; CHECK-LABEL: sst1d_d_sxtw_double: 167; CHECK: st1d { z0.d }, p0, [x0, z1.d, sxtw #3] 168; CHECK-NEXT: ret 169 call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2f64(<vscale x 2 x double> %data, 170 <vscale x 2 x i1> %pg, 171 double* %base, 172 <vscale x 2 x i32> %indices) 173 ret void 174} 175 176 177; ST1H 178declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, i16*, <vscale x 4 x i32>) 179declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i16*, <vscale x 2 x i32>) 180declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, i16*, <vscale x 4 x i32>) 181declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i16*, <vscale x 2 x i32>) 182 183; ST1W 184declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*, <vscale x 4 x i32>) 185declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32*, <vscale x 2 x i32>) 186declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*, <vscale x 4 x i32>) 187declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32*, <vscale x 2 x i32>) 188 189declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, float*, <vscale x 4 x i32>) 190declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, float*, <vscale x 4 x i32>) 191 192; ST1D 193declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*, <vscale x 2 x i32>) 194declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*, <vscale x 2 x i32>) 195 196declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*, <vscale x 2 x i32>) 197declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*, <vscale x 2 x i32>) 198