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1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -asm-verbose=0 < %s 2>%t | FileCheck %s
2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
3
4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
5; WARN-NOT: warning
6
7;
8; AESD
9;
10
11define <vscale x 16 x i8> @aesd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
12; CHECK-LABEL: aesd_i8:
13; CHECK: aesd z0.b, z0.b, z1.b
14; CHECK-NEXT: ret
15  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> %a,
16                                                        <vscale x 16 x i8> %b)
17  ret <vscale x 16 x i8> %out
18}
19
20;
21; AESIMC
22;
23
24define <vscale x 16 x i8> @aesimc_i8(<vscale x 16 x i8> %a) {
25; CHECK-LABEL: aesimc_i8:
26; CHECK: aesimc z0.b, z0.b
27; CHECK-NEXT: ret
28  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesimc(<vscale x 16 x i8> %a)
29  ret <vscale x 16 x i8> %out
30}
31
32;
33; AESE
34;
35
36define <vscale x 16 x i8> @aese_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
37; CHECK-LABEL: aese_i8:
38; CHECK: aese z0.b, z0.b, z1.b
39; CHECK-NEXT: ret
40  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8> %a,
41                                                        <vscale x 16 x i8> %b)
42  ret <vscale x 16 x i8> %out
43}
44
45;
46; AESMC
47;
48
49define <vscale x 16 x i8> @aesmc_i8(<vscale x 16 x i8> %a) {
50; CHECK-LABEL: aesmc_i8:
51; CHECK: aesmc z0.b, z0.b
52; CHECK-NEXT: ret
53  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesmc(<vscale x 16 x i8> %a)
54  ret <vscale x 16 x i8> %out
55}
56
57;
58; RAX1
59;
60
61define <vscale x 2 x i64> @rax1_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
62; CHECK-LABEL: rax1_i64:
63; CHECK: rax1 z0.d, z0.d, z1.d
64; CHECK-NEXT: ret
65  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.rax1(<vscale x 2 x i64> %a,
66                                                        <vscale x 2 x i64> %b)
67  ret <vscale x 2 x i64> %out
68}
69
70;
71; SM4E
72;
73
74define <vscale x 4 x i32> @sm4e_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
75; CHECK-LABEL: sm4e_i32:
76; CHECK: sm4e z0.s, z0.s, z1.s
77; CHECK-NEXT: ret
78  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sm4e(<vscale x 4 x i32> %a,
79                                                        <vscale x 4 x i32> %b)
80  ret <vscale x 4 x i32> %out
81}
82
83;
84; SM4EKEY
85;
86
87define <vscale x 4 x i32> @sm4ekey_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
88; CHECK-LABEL: sm4ekey_i32:
89; CHECK: sm4ekey z0.s, z0.s, z1.s
90; CHECK-NEXT: ret
91  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sm4ekey(<vscale x 4 x i32> %a,
92                                                           <vscale x 4 x i32> %b)
93  ret <vscale x 4 x i32> %out
94}
95
96
97declare <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8>, <vscale x 16 x i8>)
98declare <vscale x 16 x i8> @llvm.aarch64.sve.aesimc(<vscale x 16 x i8>)
99declare <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8>, <vscale x 16 x i8>)
100declare <vscale x 16 x i8> @llvm.aarch64.sve.aesmc(<vscale x 16 x i8>)
101declare <vscale x 2 x i64> @llvm.aarch64.sve.rax1(<vscale x 2 x i64>, <vscale x 2 x i64>)
102declare <vscale x 4 x i32> @llvm.aarch64.sve.sm4e(<vscale x 4 x i32>, <vscale x 4 x i32>)
103declare <vscale x 4 x i32> @llvm.aarch64.sve.sm4ekey(<vscale x 4 x i32>, <vscale x 4 x i32>)
104