1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s 2>%t | FileCheck %s 2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 3 4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 5; WARN-NOT: warning 6 7; 8; STNT1B, STNT1W, STNT1H, STNT1D: vector base + scalar offset 9; stnt1b { z0.s }, p0/z, [z0.s, x0] 10; 11 12; STNT1B 13define void @stnt1b_s(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) { 14; CHECK-LABEL: stnt1b_s: 15; CHECK: stnt1b { z0.s }, p0, [z1.s, x0] 16; CHECK-NEXT: ret 17 %data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8> 18 call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32(<vscale x 4 x i8> %data_trunc, 19 <vscale x 4 x i1> %pg, 20 <vscale x 4 x i32> %base, 21 i64 %offset) 22 ret void 23} 24 25define void @stnt1b_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 26; CHECK-LABEL: stnt1b_d: 27; CHECK: stnt1b { z0.d }, p0, [z1.d, x0] 28; CHECK-NEXT: ret 29 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8> 30 call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i8> %data_trunc, 31 <vscale x 2 x i1> %pg, 32 <vscale x 2 x i64> %base, 33 i64 %offset) 34 ret void 35} 36 37; STNT1H 38define void @stnt1h_s(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) { 39; CHECK-LABEL: stnt1h_s: 40; CHECK: stnt1h { z0.s }, p0, [z1.s, x0] 41; CHECK-NEXT: ret 42 %data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16> 43 call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16> %data_trunc, 44 <vscale x 4 x i1> %pg, 45 <vscale x 4 x i32> %base, 46 i64 %offset) 47 ret void 48} 49 50define void @stnt1h_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 51; CHECK-LABEL: stnt1h_d: 52; CHECK: stnt1h { z0.d }, p0, [z1.d, x0] 53; CHECK-NEXT: ret 54 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16> 55 call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i16> %data_trunc, 56 <vscale x 2 x i1> %pg, 57 <vscale x 2 x i64> %base, 58 i64 %offset) 59 ret void 60} 61 62; STNT1W 63define void @stnt1w_s(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) { 64; CHECK-LABEL: stnt1w_s: 65; CHECK: stnt1w { z0.s }, p0, [z1.s, x0] 66; CHECK-NEXT: ret 67 call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32(<vscale x 4 x i32> %data, 68 <vscale x 4 x i1> %pg, 69 <vscale x 4 x i32> %base, 70 i64 %offset) 71 ret void 72} 73 74define void @stnt1w_f32_s(<vscale x 4 x float> %data, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) { 75; CHECK-LABEL: stnt1w_f32_s: 76; CHECK: stnt1w { z0.s }, p0, [z1.s, x0] 77; CHECK-NEXT: ret 78 call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4f32.nxv4i32(<vscale x 4 x float> %data, 79 <vscale x 4 x i1> %pg, 80 <vscale x 4 x i32> %base, 81 i64 %offset) 82 ret void 83} 84 85define void @stnt1w_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 86; CHECK-LABEL: stnt1w_d: 87; CHECK: stnt1w { z0.d }, p0, [z1.d, x0] 88; CHECK-NEXT: ret 89 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32> 90 call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %data_trunc, 91 <vscale x 2 x i1> %pg, 92 <vscale x 2 x i64> %base, 93 i64 %offset) 94 ret void 95} 96 97; STNT1D 98define void @stnt1d_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 99; CHECK-LABEL: stnt1d_d: 100; CHECK: stnt1d { z0.d }, p0, [z1.d, x0] 101; CHECK-NEXT: ret 102 call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %data, 103 <vscale x 2 x i1> %pg, 104 <vscale x 2 x i64> %base, 105 i64 %offset) 106 ret void 107} 108 109define void @stnt1d_f64_d(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) { 110; CHECK-LABEL: stnt1d_f64_d: 111; CHECK: stnt1d { z0.d }, p0, [z1.d, x0] 112; CHECK-NEXT: ret 113 call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f64.nxv2i64(<vscale x 2 x double> %data, 114 <vscale x 2 x i1> %pg, 115 <vscale x 2 x i64> %base, 116 i64 %offset) 117 ret void 118} 119 120; STNT1B 121declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i8>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64) 122declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32(<vscale x 4 x i8>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64) 123 124; STNT1H 125declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i16>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64) 126declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64) 127 128; STNT1W 129declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64) 130declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64) 131 132declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4f32.nxv4i32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64) 133 134; STNT1D 135declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64) 136 137declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f32.nxv2i64(<vscale x 2 x float>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64) 138declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f64.nxv2i64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64) 139