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1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s 2>%t | FileCheck %s
2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
3
4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
5; WARN-NOT: warning
6
7;
8; TBL2
9;
10
11define <vscale x 16 x i8> @tbl2_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %unused,
12                                  <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
13; CHECK-LABEL: tbl2_b:
14; CHECK: mov z1.d, z0.d
15; CHECK-NEXT: tbl z0.b, { z1.b, z2.b }, z3.b
16; CHECK-NEXT: ret
17  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.tbl2.nxv16i8(<vscale x 16 x i8> %a,
18                                                                <vscale x 16 x i8> %b,
19                                                                <vscale x 16 x i8> %c)
20  ret <vscale x 16 x i8> %out
21}
22
23define <vscale x 8 x i16> @tbl2_h(<vscale x 8 x i16> %a, <vscale x 16 x i8> %unused,
24                                  <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
25; CHECK-LABEL: tbl2_h:
26; CHECK: mov z1.d, z0.d
27; CHECK-NEXT: tbl z0.h, { z1.h, z2.h }, z3.h
28; CHECK-NEXT: ret
29  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.tbl2.nxv8i16(<vscale x 8 x i16> %a,
30                                                                <vscale x 8 x i16> %b,
31                                                                <vscale x 8 x i16> %c)
32  ret <vscale x 8 x i16> %out
33}
34
35define <vscale x 4 x i32> @tbl2_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %unused,
36                                  <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
37; CHECK-LABEL: tbl2_s:
38; CHECK: mov z1.d, z0.d
39; CHECK-NEXT: tbl z0.s, { z1.s, z2.s }, z3.s
40; CHECK-NEXT: ret
41  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.tbl2.nxv4i32(<vscale x 4 x i32> %a,
42                                                                <vscale x 4 x i32> %b,
43                                                                <vscale x 4 x i32> %c)
44  ret <vscale x 4 x i32> %out
45}
46
47define <vscale x 2 x i64> @tbl2_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %unused,
48                                  <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
49; CHECK-LABEL: tbl2_d:
50; CHECK: mov z1.d, z0.d
51; CHECK-NEXT: tbl z0.d, { z1.d, z2.d }, z3.d
52; CHECK-NEXT: ret
53  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.tbl2.nxv2i64(<vscale x 2 x i64> %a,
54                                                                <vscale x 2 x i64> %b,
55                                                                <vscale x 2 x i64> %c)
56  ret <vscale x 2 x i64> %out
57}
58
59define <vscale x 8 x half> @tbl2_fh(<vscale x 8 x half> %a, <vscale x 8 x half> %unused,
60                                    <vscale x 8 x half> %b, <vscale x 8 x i16> %c) {
61; CHECK-LABEL: tbl2_fh:
62; CHECK: mov z1.d, z0.d
63; CHECK-NEXT: tbl z0.h, { z1.h, z2.h }, z3.h
64; CHECK-NEXT: ret
65  %out = call <vscale x 8 x half> @llvm.aarch64.sve.tbl2.nxv8f16(<vscale x 8 x half> %a,
66                                                                 <vscale x 8 x half> %b,
67                                                                 <vscale x 8 x i16> %c)
68  ret <vscale x 8 x half> %out
69}
70
71define <vscale x 4 x float> @tbl2_fs(<vscale x 4 x float> %a, <vscale x 4 x float> %unused,
72                                     <vscale x 4 x float> %b, <vscale x 4 x i32> %c) {
73; CHECK-LABEL: tbl2_fs:
74; CHECK: mov z1.d, z0.d
75; CHECK-NEXT: tbl z0.s, { z1.s, z2.s }, z3.s
76; CHECK-NEXT: ret
77  %out = call <vscale x 4 x float> @llvm.aarch64.sve.tbl2.nxv4f32(<vscale x 4 x float> %a,
78                                                                  <vscale x 4 x float> %b,
79                                                                  <vscale x 4 x i32> %c)
80  ret <vscale x 4 x float> %out
81}
82
83define <vscale x 2 x double> @tbl2_fd(<vscale x 2 x double> %a, <vscale x 2 x double> %unused,
84                                      <vscale x 2 x double> %b, <vscale x 2 x i64> %c) {
85; CHECK-LABEL: tbl2_fd:
86; CHECK: mov z1.d, z0.d
87; CHECK-NEXT: tbl z0.d, { z1.d, z2.d }, z3.d
88; CHECK-NEXT: ret
89  %out = call <vscale x 2 x double> @llvm.aarch64.sve.tbl2.nxv2f64(<vscale x 2 x double> %a,
90                                                                   <vscale x 2 x double> %b,
91                                                                   <vscale x 2 x i64> %c)
92  ret <vscale x 2 x double> %out
93}
94
95;
96; TBX
97;
98
99define <vscale x 16 x i8> @tbx_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
100; CHECK-LABEL: tbx_b:
101; CHECK: tbx z0.b, z1.b, z2.b
102; CHECK-NEXT: ret
103  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.tbx.nxv16i8(<vscale x 16 x i8> %a,
104                                                               <vscale x 16 x i8> %b,
105                                                               <vscale x 16 x i8> %c)
106  ret <vscale x 16 x i8> %out
107}
108
109define <vscale x 8 x i16> @tbx_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
110; CHECK-LABEL: tbx_h:
111; CHECK: tbx z0.h, z1.h, z2.h
112; CHECK-NEXT: ret
113  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.tbx.nxv8i16(<vscale x 8 x i16> %a,
114                                                               <vscale x 8 x i16> %b,
115                                                               <vscale x 8 x i16> %c)
116  ret <vscale x 8 x i16> %out
117}
118
119define <vscale x 8 x half> @ftbx_h(<vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x i16> %c) {
120; CHECK-LABEL: ftbx_h:
121; CHECK: tbx z0.h, z1.h, z2.h
122; CHECK-NEXT: ret
123  %out = call <vscale x 8 x half> @llvm.aarch64.sve.tbx.nxv8f16(<vscale x 8 x half> %a,
124                                                                <vscale x 8 x half> %b,
125                                                                <vscale x 8 x i16> %c)
126  ret <vscale x 8 x half> %out
127}
128
129define <vscale x 8 x bfloat> @ftbx_h_bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x i16> %c) #0 {
130; CHECK-LABEL: ftbx_h_bf16:
131; CHECK: tbx z0.h, z1.h, z2.h
132; CHECK-NEXT: ret
133  %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tbx.nxv8bf16(<vscale x 8 x bfloat> %a,
134                                                                   <vscale x 8 x bfloat> %b,
135                                                                   <vscale x 8 x i16> %c)
136  ret <vscale x 8 x bfloat> %out
137}
138
139define <vscale x 4 x i32> @tbx_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
140; CHECK-LABEL: tbx_s:
141; CHECK: tbx z0.s, z1.s, z2.s
142; CHECK-NEXT: ret
143  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.tbx.nxv4i32(<vscale x 4 x i32> %a,
144                                                               <vscale x 4 x i32> %b,
145                                                               <vscale x 4 x i32> %c)
146  ret <vscale x 4 x i32> %out
147}
148
149define <vscale x 4 x float> @ftbx_s(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x i32> %c) {
150; CHECK-LABEL: ftbx_s:
151; CHECK: tbx z0.s, z1.s, z2.s
152; CHECK-NEXT: ret
153  %out = call <vscale x 4 x float> @llvm.aarch64.sve.tbx.nxv4f32(<vscale x 4 x float> %a,
154                                                                 <vscale x 4 x float> %b,
155                                                                 <vscale x 4 x i32> %c)
156  ret <vscale x 4 x float> %out
157}
158
159define <vscale x 2 x i64> @tbx_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
160; CHECK-LABEL: tbx_d:
161; CHECK: tbx z0.d, z1.d, z2.d
162; CHECK-NEXT: ret
163  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.tbx.nxv2i64(<vscale x 2 x i64> %a,
164                                                               <vscale x 2 x i64> %b,
165                                                               <vscale x 2 x i64> %c)
166  ret <vscale x 2 x i64> %out
167}
168
169define <vscale x 2 x double> @ftbx_d(<vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x i64> %c) {
170; CHECK-LABEL: ftbx_d:
171; CHECK: tbx z0.d, z1.d, z2.d
172; CHECK-NEXT: ret
173  %out = call <vscale x 2 x double> @llvm.aarch64.sve.tbx.nxv2f64(<vscale x 2 x double> %a,
174                                                                  <vscale x 2 x double> %b,
175                                                                  <vscale x 2 x i64> %c)
176  ret <vscale x 2 x double> %out
177}
178
179declare <vscale x 16 x i8> @llvm.aarch64.sve.tbl2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
180declare <vscale x 8 x i16> @llvm.aarch64.sve.tbl2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
181declare <vscale x 4 x i32> @llvm.aarch64.sve.tbl2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
182declare <vscale x 2 x i64> @llvm.aarch64.sve.tbl2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
183
184declare <vscale x 8 x half> @llvm.aarch64.sve.tbl2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>)
185declare <vscale x 4 x float> @llvm.aarch64.sve.tbl2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i32>)
186declare <vscale x 2 x double> @llvm.aarch64.sve.tbl2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i64>)
187
188declare <vscale x 16 x i8> @llvm.aarch64.sve.tbx.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
189declare <vscale x 8 x i16> @llvm.aarch64.sve.tbx.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
190declare <vscale x 4 x i32> @llvm.aarch64.sve.tbx.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
191declare <vscale x 2 x i64> @llvm.aarch64.sve.tbx.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
192
193declare <vscale x 8 x half> @llvm.aarch64.sve.tbx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>)
194declare <vscale x 4 x float> @llvm.aarch64.sve.tbx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i32>)
195declare <vscale x 2 x double> @llvm.aarch64.sve.tbx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i64>)
196
197declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tbx.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>)
198
199; +bf16 is required for the bfloat version.
200attributes #0 = { "target-features"="+sve,+bf16" }
201