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1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s 2>%t | FileCheck %s
2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
3
4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
5; WARN-NOT: warning
6
7;
8; SQXTNB
9;
10
11define <vscale x 16 x i8> @sqxtnb_h(<vscale x 8 x i16> %a) {
12; CHECK-LABEL: sqxtnb_h:
13; CHECK: sqxtnb z0.b, z0.h
14; CHECK-NEXT: ret
15  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnb.nxv8i16(<vscale x 8 x i16> %a)
16  ret <vscale x 16 x i8> %out
17}
18
19define <vscale x 8 x i16> @sqxtnb_s(<vscale x 4 x i32> %a) {
20; CHECK-LABEL: sqxtnb_s:
21; CHECK: sqxtnb z0.h, z0.s
22; CHECK-NEXT: ret
23  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnb.nxv4i32(<vscale x 4 x i32> %a)
24  ret <vscale x 8 x i16> %out
25}
26
27define <vscale x 4 x i32> @sqxtnb_d(<vscale x 2 x i64> %a) {
28; CHECK-LABEL: sqxtnb_d:
29; CHECK: sqxtnb z0.s, z0.d
30; CHECK-NEXT: ret
31  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnb.nxv2i64(<vscale x 2 x i64> %a)
32  ret <vscale x 4 x i32> %out
33}
34
35;
36; UQXTNB
37;
38
39define <vscale x 16 x i8> @uqxtnb_h(<vscale x 8 x i16> %a) {
40; CHECK-LABEL: uqxtnb_h:
41; CHECK: uqxtnb z0.b, z0.h
42; CHECK-NEXT: ret
43  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnb.nxv8i16(<vscale x 8 x i16> %a)
44  ret <vscale x 16 x i8> %out
45}
46
47define <vscale x 8 x i16> @uqxtnb_s(<vscale x 4 x i32> %a) {
48; CHECK-LABEL: uqxtnb_s:
49; CHECK: uqxtnb z0.h, z0.s
50; CHECK-NEXT: ret
51  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnb.nxv4i32(<vscale x 4 x i32> %a)
52  ret <vscale x 8 x i16> %out
53}
54
55define <vscale x 4 x i32> @uqxtnb_d(<vscale x 2 x i64> %a) {
56; CHECK-LABEL: uqxtnb_d:
57; CHECK: uqxtnb z0.s, z0.d
58; CHECK-NEXT: ret
59  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnb.nxv2i64(<vscale x 2 x i64> %a)
60  ret <vscale x 4 x i32> %out
61}
62
63;
64; SQXTUNB
65;
66
67define <vscale x 16 x i8> @sqxtunb_h(<vscale x 8 x i16> %a) {
68; CHECK-LABEL: sqxtunb_h:
69; CHECK: sqxtunb z0.b, z0.h
70; CHECK-NEXT: ret
71  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunb.nxv8i16(<vscale x 8 x i16> %a)
72  ret <vscale x 16 x i8> %out
73}
74
75define <vscale x 8 x i16> @sqxtunb_s(<vscale x 4 x i32> %a) {
76; CHECK-LABEL: sqxtunb_s:
77; CHECK: sqxtunb z0.h, z0.s
78; CHECK-NEXT: ret
79  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunb.nxv4i32(<vscale x 4 x i32> %a)
80  ret <vscale x 8 x i16> %out
81}
82
83define <vscale x 4 x i32> @sqxtunb_d(<vscale x 2 x i64> %a) {
84; CHECK-LABEL: sqxtunb_d:
85; CHECK: sqxtunb z0.s, z0.d
86; CHECK-NEXT: ret
87  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunb.nxv2i64(<vscale x 2 x i64> %a)
88  ret <vscale x 4 x i32> %out
89}
90
91;
92; SQXTNT
93;
94
95define <vscale x 16 x i8> @sqxtnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
96; CHECK-LABEL: sqxtnt_h:
97; CHECK: sqxtnt z0.b, z1.h
98; CHECK-NEXT: ret
99  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnt.nxv8i16(<vscale x 16 x i8> %a,
100                                                             <vscale x 8 x i16> %b)
101  ret <vscale x 16 x i8> %out
102}
103
104define <vscale x 8 x i16> @sqxtnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
105; CHECK-LABEL: sqxtnt_s:
106; CHECK: sqxtnt z0.h, z1.s
107; CHECK-NEXT: ret
108  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnt.nxv4i32(<vscale x 8 x i16> %a,
109                                                             <vscale x 4 x i32> %b)
110  ret <vscale x 8 x i16> %out
111}
112
113define <vscale x 4 x i32> @sqxtnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
114; CHECK-LABEL: sqxtnt_d:
115; CHECK: sqxtnt z0.s, z1.d
116; CHECK-NEXT: ret
117  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnt.nxv2i64(<vscale x 4 x i32> %a,
118                                                             <vscale x 2 x i64> %b)
119  ret <vscale x 4 x i32> %out
120}
121
122;
123; UQXTNT
124;
125
126define <vscale x 16 x i8> @uqxtnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
127; CHECK-LABEL: uqxtnt_h:
128; CHECK: uqxtnt z0.b, z1.h
129; CHECK-NEXT: ret
130  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnt.nxv8i16(<vscale x 16 x i8> %a,
131                                                             <vscale x 8 x i16> %b)
132  ret <vscale x 16 x i8> %out
133}
134
135define <vscale x 8 x i16> @uqxtnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
136; CHECK-LABEL: uqxtnt_s:
137; CHECK: uqxtnt z0.h, z1.s
138; CHECK-NEXT: ret
139  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnt.nxv4i32(<vscale x 8 x i16> %a,
140                                                             <vscale x 4 x i32> %b)
141  ret <vscale x 8 x i16> %out
142}
143
144define <vscale x 4 x i32> @uqxtnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
145; CHECK-LABEL: uqxtnt_d:
146; CHECK: uqxtnt z0.s, z1.d
147; CHECK-NEXT: ret
148  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnt.nxv2i64(<vscale x 4 x i32> %a,
149                                                             <vscale x 2 x i64> %b)
150  ret <vscale x 4 x i32> %out
151}
152
153;
154; SQXTUNT
155;
156
157define <vscale x 16 x i8> @sqxtunt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
158; CHECK-LABEL: sqxtunt_h:
159; CHECK: sqxtunt z0.b, z1.h
160; CHECK-NEXT: ret
161  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunt.nxv8i16(<vscale x 16 x i8> %a,
162                                                              <vscale x 8 x i16> %b)
163  ret <vscale x 16 x i8> %out
164}
165
166define <vscale x 8 x i16> @sqxtunt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
167; CHECK-LABEL: sqxtunt_s:
168; CHECK: sqxtunt z0.h, z1.s
169; CHECK-NEXT: ret
170  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunt.nxv4i32(<vscale x 8 x i16> %a,
171                                                              <vscale x 4 x i32> %b)
172  ret <vscale x 8 x i16> %out
173}
174
175define <vscale x 4 x i32> @sqxtunt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
176; CHECK-LABEL: sqxtunt_d:
177; CHECK: sqxtunt z0.s, z1.d
178; CHECK-NEXT: ret
179  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunt.nxv2i64(<vscale x 4 x i32> %a,
180                                                              <vscale x 2 x i64> %b)
181  ret <vscale x 4 x i32> %out
182}
183
184declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnb.nxv8i16(<vscale x 8 x i16>)
185declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnb.nxv4i32(<vscale x 4 x i32>)
186declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnb.nxv2i64(<vscale x 2 x i64>)
187
188declare <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnb.nxv8i16(<vscale x 8 x i16>)
189declare <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnb.nxv4i32(<vscale x 4 x i32>)
190declare <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnb.nxv2i64(<vscale x 2 x i64>)
191
192declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunb.nxv8i16(<vscale x 8 x i16>)
193declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunb.nxv4i32(<vscale x 4 x i32>)
194declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunb.nxv2i64(<vscale x 2 x i64>)
195
196declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>)
197declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>)
198declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>)
199
200declare <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>)
201declare <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>)
202declare <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>)
203
204declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>)
205declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>)
206declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>)
207