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1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -asm-verbose=0 -mattr=+use-experimental-zeroing-pseudos < %s 2>%t | FileCheck %s
2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
3
4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
5; WARN-NOT: warning
6
7;
8; SQSHLU
9;
10
11define <vscale x 16 x i8> @sqshlu_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
12; CHECK-LABEL: sqshlu_i8:
13; CHECK:      movprfx z0.b, p0/z, z0.b
14; CHECK-NEXT: sqshlu z0.b, p0/m, z0.b, #2
15; CHECK-NEXT: ret
16  %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
17  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshlu.nxv16i8(<vscale x 16 x i1> %pg,
18                                                                  <vscale x 16 x i8> %a_z,
19                                                                  i32 2)
20  ret <vscale x 16 x i8> %out
21}
22
23define <vscale x 8 x i16> @sqshlu_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
24; CHECK-LABEL: sqshlu_i16:
25; CHECK:      movprfx z0.h, p0/z, z0.h
26; CHECK-NEXT: sqshlu z0.h, p0/m, z0.h, #3
27; CHECK-NEXT: ret
28  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
29  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshlu.nxv8i16(<vscale x 8 x i1> %pg,
30                                                                  <vscale x 8 x i16> %a_z,
31                                                                  i32 3)
32  ret <vscale x 8 x i16> %out
33}
34
35define <vscale x 4 x i32> @sqshlu_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
36; CHECK-LABEL: sqshlu_i32:
37; CHECK:      movprfx z0.s, p0/z, z0.s
38; CHECK-NEXT: sqshlu z0.s, p0/m, z0.s, #29
39; CHECK-NEXT: ret
40  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
41  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshlu.nxv4i32(<vscale x 4 x i1> %pg,
42                                                                  <vscale x 4 x i32> %a_z,
43                                                                  i32 29)
44  ret <vscale x 4 x i32> %out
45}
46
47define <vscale x 2 x i64> @sqshlu_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
48; CHECK-LABEL: sqshlu_i64:
49; CHECK:      movprfx z0.d, p0/z, z0.d
50; CHECK-NEXT: sqshlu z0.d, p0/m, z0.d, #62
51; CHECK-NEXT: ret
52  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
53  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqshlu.nxv2i64(<vscale x 2 x i1> %pg,
54                                                                  <vscale x 2 x i64> %a_z,
55                                                                  i32 62)
56  ret <vscale x 2 x i64> %out
57}
58
59declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshlu.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32)
60declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshlu.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32)
61declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshlu.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32)
62declare <vscale x 2 x i64> @llvm.aarch64.sve.sqshlu.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32)
63