1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK 3 4; Same as vecreduce-fmul-legalization.ll, but without fmf. 5 6declare half @llvm.vector.reduce.fmul.f16.v1f16(half, <1 x half>) 7declare float @llvm.vector.reduce.fmul.f32.v1f32(float, <1 x float>) 8declare double @llvm.vector.reduce.fmul.f64.v1f64(double, <1 x double>) 9declare fp128 @llvm.vector.reduce.fmul.f128.v1f128(fp128, <1 x fp128>) 10 11declare float @llvm.vector.reduce.fmul.f32.v3f32(float, <3 x float>) 12declare fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128, <2 x fp128>) 13declare float @llvm.vector.reduce.fmul.f32.v16f32(float, <16 x float>) 14 15define half @test_v1f16(<1 x half> %a) nounwind { 16; CHECK-LABEL: test_v1f16: 17; CHECK: // %bb.0: 18; CHECK-NEXT: ret 19 %b = call half @llvm.vector.reduce.fmul.f16.v1f16(half 1.0, <1 x half> %a) 20 ret half %b 21} 22 23define float @test_v1f32(<1 x float> %a) nounwind { 24; CHECK-LABEL: test_v1f32: 25; CHECK: // %bb.0: 26; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 27; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 28; CHECK-NEXT: ret 29 %b = call float @llvm.vector.reduce.fmul.f32.v1f32(float 1.0, <1 x float> %a) 30 ret float %b 31} 32 33define double @test_v1f64(<1 x double> %a) nounwind { 34; CHECK-LABEL: test_v1f64: 35; CHECK: // %bb.0: 36; CHECK-NEXT: ret 37 %b = call double @llvm.vector.reduce.fmul.f64.v1f64(double 1.0, <1 x double> %a) 38 ret double %b 39} 40 41define fp128 @test_v1f128(<1 x fp128> %a) nounwind { 42; CHECK-LABEL: test_v1f128: 43; CHECK: // %bb.0: 44; CHECK-NEXT: ret 45 %b = call fp128 @llvm.vector.reduce.fmul.f128.v1f128(fp128 0xL00000000000000003fff00000000000000, <1 x fp128> %a) 46 ret fp128 %b 47} 48 49define float @test_v3f32(<3 x float> %a) nounwind { 50; CHECK-LABEL: test_v3f32: 51; CHECK: // %bb.0: 52; CHECK-NEXT: fmul s1, s0, v0.s[1] 53; CHECK-NEXT: fmul s0, s1, v0.s[2] 54; CHECK-NEXT: ret 55 %b = call float @llvm.vector.reduce.fmul.f32.v3f32(float 1.0, <3 x float> %a) 56 ret float %b 57} 58 59define fp128 @test_v2f128(<2 x fp128> %a) nounwind { 60; CHECK-LABEL: test_v2f128: 61; CHECK: // %bb.0: 62; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill 63; CHECK-NEXT: bl __multf3 64; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload 65; CHECK-NEXT: ret 66 %b = call fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128 0xL00000000000000003fff00000000000000, <2 x fp128> %a) 67 ret fp128 %b 68} 69 70define float @test_v16f32(<16 x float> %a) nounwind { 71; CHECK-LABEL: test_v16f32: 72; CHECK: // %bb.0: 73; CHECK-NEXT: fmul s4, s0, v0.s[1] 74; CHECK-NEXT: fmul s4, s4, v0.s[2] 75; CHECK-NEXT: fmul s0, s4, v0.s[3] 76; CHECK-NEXT: fmul s0, s0, v1.s[0] 77; CHECK-NEXT: fmul s0, s0, v1.s[1] 78; CHECK-NEXT: fmul s0, s0, v1.s[2] 79; CHECK-NEXT: fmul s0, s0, v1.s[3] 80; CHECK-NEXT: fmul s0, s0, v2.s[0] 81; CHECK-NEXT: fmul s0, s0, v2.s[1] 82; CHECK-NEXT: fmul s0, s0, v2.s[2] 83; CHECK-NEXT: fmul s0, s0, v2.s[3] 84; CHECK-NEXT: fmul s0, s0, v3.s[0] 85; CHECK-NEXT: fmul s0, s0, v3.s[1] 86; CHECK-NEXT: fmul s0, s0, v3.s[2] 87; CHECK-NEXT: fmul s0, s0, v3.s[3] 88; CHECK-NEXT: ret 89 %b = call float @llvm.vector.reduce.fmul.f32.v16f32(float 1.0, <16 x float> %a) 90 ret float %b 91} 92