1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3 4; End to end tests for scalar vs. vector boolean legalization strategies. 5 6define amdgpu_ps float @select_vgpr_sgpr_trunc_cond(i32 inreg %a, i32 %b, i32 %c) { 7; GCN-LABEL: select_vgpr_sgpr_trunc_cond: 8; GCN: ; %bb.0: 9; GCN-NEXT: s_and_b32 s0, 1, s0 10; GCN-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 11; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 12; GCN-NEXT: ; return to shader part epilog 13 %cc = trunc i32 %a to i1 14 %r = select i1 %cc, i32 %b, i32 %c 15 %r.f = bitcast i32 %r to float 16 ret float %r.f 17} 18 19define amdgpu_ps float @select_vgpr_sgpr_trunc_and_cond(i32 inreg %a.0, i32 inreg %a.1, i32 %b, i32 %c) { 20; GCN-LABEL: select_vgpr_sgpr_trunc_and_cond: 21; GCN: ; %bb.0: 22; GCN-NEXT: s_and_b32 s0, s0, s1 23; GCN-NEXT: s_and_b32 s0, 1, s0 24; GCN-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 25; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 26; GCN-NEXT: ; return to shader part epilog 27 %cc.0 = trunc i32 %a.0 to i1 28 %cc.1 = trunc i32 %a.1 to i1 29 %and = and i1 %cc.0, %cc.1 30 %r = select i1 %and, i32 %b, i32 %c 31 %r.f = bitcast i32 %r to float 32 ret float %r.f 33} 34 35define amdgpu_ps i32 @select_sgpr_trunc_and_cond(i32 inreg %a.0, i32 inreg %a.1, i32 inreg %b, i32 inreg %c) { 36; GCN-LABEL: select_sgpr_trunc_and_cond: 37; GCN: ; %bb.0: 38; GCN-NEXT: s_and_b32 s0, s0, s1 39; GCN-NEXT: s_and_b32 s0, s0, 1 40; GCN-NEXT: s_cmp_lg_u32 s0, 0 41; GCN-NEXT: s_cselect_b32 s0, s2, s3 42; GCN-NEXT: ; return to shader part epilog 43 %cc.0 = trunc i32 %a.0 to i1 44 %cc.1 = trunc i32 %a.1 to i1 45 %and = and i1 %cc.0, %cc.1 46 %r = select i1 %and, i32 %b, i32 %c 47 ret i32 %r 48} 49 50define amdgpu_kernel void @sgpr_trunc_brcond(i32 %cond) { 51; GCN-LABEL: sgpr_trunc_brcond: 52; GCN: ; %bb.0: ; %entry 53; GCN-NEXT: s_load_dword s0, s[0:1], 0x9 54; GCN-NEXT: s_waitcnt lgkmcnt(0) 55; GCN-NEXT: s_xor_b32 s0, s0, -1 56; GCN-NEXT: s_and_b32 s0, s0, 1 57; GCN-NEXT: s_cmp_lg_u32 s0, 0 58; GCN-NEXT: s_cbranch_scc1 BB3_2 59; GCN-NEXT: ; %bb.1: ; %bb0 60; GCN-NEXT: v_mov_b32_e32 v0, 0 61; GCN-NEXT: flat_store_dword v[0:1], v0 62; GCN-NEXT: BB3_2: ; %bb1 63; GCN-NEXT: v_mov_b32_e32 v0, 1 64; GCN-NEXT: flat_store_dword v[0:1], v0 65entry: 66 %trunc = trunc i32 %cond to i1 67 br i1 %trunc, label %bb0, label %bb1 68 69bb0: 70 store volatile i32 0, i32 addrspace(1)* undef 71 unreachable 72 73bb1: 74 store volatile i32 1, i32 addrspace(1)* undef 75 unreachable 76} 77 78define amdgpu_kernel void @brcond_sgpr_trunc_and(i32 %cond0, i32 %cond1) { 79; GCN-LABEL: brcond_sgpr_trunc_and: 80; GCN: ; %bb.0: ; %entry 81; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 82; GCN-NEXT: s_waitcnt lgkmcnt(0) 83; GCN-NEXT: s_and_b32 s0, s0, s1 84; GCN-NEXT: s_xor_b32 s0, s0, -1 85; GCN-NEXT: s_and_b32 s0, s0, 1 86; GCN-NEXT: s_cmp_lg_u32 s0, 0 87; GCN-NEXT: s_cbranch_scc1 BB4_2 88; GCN-NEXT: ; %bb.1: ; %bb0 89; GCN-NEXT: v_mov_b32_e32 v0, 0 90; GCN-NEXT: flat_store_dword v[0:1], v0 91; GCN-NEXT: BB4_2: ; %bb1 92; GCN-NEXT: v_mov_b32_e32 v0, 1 93; GCN-NEXT: flat_store_dword v[0:1], v0 94entry: 95 %trunc0 = trunc i32 %cond0 to i1 96 %trunc1 = trunc i32 %cond1 to i1 97 %and = and i1 %trunc0, %trunc1 98 br i1 %and, label %bb0, label %bb1 99 100bb0: 101 store volatile i32 0, i32 addrspace(1)* undef 102 unreachable 103 104bb1: 105 store volatile i32 1, i32 addrspace(1)* undef 106 unreachable 107} 108