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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
4
5define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, i32 %s) {
6; GFX9-LABEL: load_mip_1d:
7; GFX9:       ; %bb.0: ; %main_body
8; GFX9-NEXT:    s_mov_b32 s0, s2
9; GFX9-NEXT:    s_mov_b32 s1, s3
10; GFX9-NEXT:    s_mov_b32 s2, s4
11; GFX9-NEXT:    s_mov_b32 s3, s5
12; GFX9-NEXT:    s_mov_b32 s4, s6
13; GFX9-NEXT:    s_mov_b32 s5, s7
14; GFX9-NEXT:    s_mov_b32 s6, s8
15; GFX9-NEXT:    s_mov_b32 s7, s9
16; GFX9-NEXT:    image_load v[0:3], v0, s[0:7] dmask:0xf unorm
17; GFX9-NEXT:    s_waitcnt vmcnt(0)
18; GFX9-NEXT:    ; return to shader part epilog
19;
20; GFX10-LABEL: load_mip_1d:
21; GFX10:       ; %bb.0: ; %main_body
22; GFX10-NEXT:    s_mov_b32 s0, s2
23; GFX10-NEXT:    s_mov_b32 s1, s3
24; GFX10-NEXT:    s_mov_b32 s2, s4
25; GFX10-NEXT:    s_mov_b32 s3, s5
26; GFX10-NEXT:    s_mov_b32 s4, s6
27; GFX10-NEXT:    s_mov_b32 s5, s7
28; GFX10-NEXT:    s_mov_b32 s6, s8
29; GFX10-NEXT:    s_mov_b32 s7, s9
30; GFX10-NEXT:    image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
31; GFX10-NEXT:    s_waitcnt vmcnt(0)
32; GFX10-NEXT:    ; return to shader part epilog
33main_body:
34  %v = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32(i32 15, i32 %s, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
35  ret <4 x float> %v
36}
37
38define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
39; GFX9-LABEL: load_mip_2d:
40; GFX9:       ; %bb.0: ; %main_body
41; GFX9-NEXT:    s_mov_b32 s0, s2
42; GFX9-NEXT:    s_mov_b32 s1, s3
43; GFX9-NEXT:    s_mov_b32 s2, s4
44; GFX9-NEXT:    s_mov_b32 s3, s5
45; GFX9-NEXT:    s_mov_b32 s4, s6
46; GFX9-NEXT:    s_mov_b32 s5, s7
47; GFX9-NEXT:    s_mov_b32 s6, s8
48; GFX9-NEXT:    s_mov_b32 s7, s9
49; GFX9-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm
50; GFX9-NEXT:    s_waitcnt vmcnt(0)
51; GFX9-NEXT:    ; return to shader part epilog
52;
53; GFX10-LABEL: load_mip_2d:
54; GFX10:       ; %bb.0: ; %main_body
55; GFX10-NEXT:    s_mov_b32 s0, s2
56; GFX10-NEXT:    s_mov_b32 s1, s3
57; GFX10-NEXT:    s_mov_b32 s2, s4
58; GFX10-NEXT:    s_mov_b32 s3, s5
59; GFX10-NEXT:    s_mov_b32 s4, s6
60; GFX10-NEXT:    s_mov_b32 s5, s7
61; GFX10-NEXT:    s_mov_b32 s6, s8
62; GFX10-NEXT:    s_mov_b32 s7, s9
63; GFX10-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
64; GFX10-NEXT:    s_waitcnt vmcnt(0)
65; GFX10-NEXT:    ; return to shader part epilog
66main_body:
67  %v = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
68  ret <4 x float> %v
69}
70
71define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %u) {
72; GFX9-LABEL: load_mip_3d:
73; GFX9:       ; %bb.0: ; %main_body
74; GFX9-NEXT:    s_mov_b32 s0, s2
75; GFX9-NEXT:    s_mov_b32 s1, s3
76; GFX9-NEXT:    s_mov_b32 s2, s4
77; GFX9-NEXT:    s_mov_b32 s3, s5
78; GFX9-NEXT:    s_mov_b32 s4, s6
79; GFX9-NEXT:    s_mov_b32 s5, s7
80; GFX9-NEXT:    s_mov_b32 s6, s8
81; GFX9-NEXT:    s_mov_b32 s7, s9
82; GFX9-NEXT:    image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm
83; GFX9-NEXT:    s_waitcnt vmcnt(0)
84; GFX9-NEXT:    ; return to shader part epilog
85;
86; GFX10-LABEL: load_mip_3d:
87; GFX10:       ; %bb.0: ; %main_body
88; GFX10-NEXT:    s_mov_b32 s0, s2
89; GFX10-NEXT:    s_mov_b32 s1, s3
90; GFX10-NEXT:    s_mov_b32 s2, s4
91; GFX10-NEXT:    s_mov_b32 s3, s5
92; GFX10-NEXT:    s_mov_b32 s4, s6
93; GFX10-NEXT:    s_mov_b32 s5, s7
94; GFX10-NEXT:    s_mov_b32 s6, s8
95; GFX10-NEXT:    s_mov_b32 s7, s9
96; GFX10-NEXT:    image_load v[0:3], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm
97; GFX10-NEXT:    s_waitcnt vmcnt(0)
98; GFX10-NEXT:    ; return to shader part epilog
99main_body:
100  %v = call <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
101  ret <4 x float> %v
102}
103
104define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
105; GFX9-LABEL: load_mip_1darray:
106; GFX9:       ; %bb.0: ; %main_body
107; GFX9-NEXT:    s_mov_b32 s0, s2
108; GFX9-NEXT:    s_mov_b32 s1, s3
109; GFX9-NEXT:    s_mov_b32 s2, s4
110; GFX9-NEXT:    s_mov_b32 s3, s5
111; GFX9-NEXT:    s_mov_b32 s4, s6
112; GFX9-NEXT:    s_mov_b32 s5, s7
113; GFX9-NEXT:    s_mov_b32 s6, s8
114; GFX9-NEXT:    s_mov_b32 s7, s9
115; GFX9-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm da
116; GFX9-NEXT:    s_waitcnt vmcnt(0)
117; GFX9-NEXT:    ; return to shader part epilog
118;
119; GFX10-LABEL: load_mip_1darray:
120; GFX10:       ; %bb.0: ; %main_body
121; GFX10-NEXT:    s_mov_b32 s0, s2
122; GFX10-NEXT:    s_mov_b32 s1, s3
123; GFX10-NEXT:    s_mov_b32 s2, s4
124; GFX10-NEXT:    s_mov_b32 s3, s5
125; GFX10-NEXT:    s_mov_b32 s4, s6
126; GFX10-NEXT:    s_mov_b32 s5, s7
127; GFX10-NEXT:    s_mov_b32 s6, s8
128; GFX10-NEXT:    s_mov_b32 s7, s9
129; GFX10-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm
130; GFX10-NEXT:    s_waitcnt vmcnt(0)
131; GFX10-NEXT:    ; return to shader part epilog
132main_body:
133  %v = call <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i32(i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
134  ret <4 x float> %v
135}
136
137define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %u) {
138; GFX9-LABEL: load_mip_2darray:
139; GFX9:       ; %bb.0: ; %main_body
140; GFX9-NEXT:    s_mov_b32 s0, s2
141; GFX9-NEXT:    s_mov_b32 s1, s3
142; GFX9-NEXT:    s_mov_b32 s2, s4
143; GFX9-NEXT:    s_mov_b32 s3, s5
144; GFX9-NEXT:    s_mov_b32 s4, s6
145; GFX9-NEXT:    s_mov_b32 s5, s7
146; GFX9-NEXT:    s_mov_b32 s6, s8
147; GFX9-NEXT:    s_mov_b32 s7, s9
148; GFX9-NEXT:    image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm da
149; GFX9-NEXT:    s_waitcnt vmcnt(0)
150; GFX9-NEXT:    ; return to shader part epilog
151;
152; GFX10-LABEL: load_mip_2darray:
153; GFX10:       ; %bb.0: ; %main_body
154; GFX10-NEXT:    s_mov_b32 s0, s2
155; GFX10-NEXT:    s_mov_b32 s1, s3
156; GFX10-NEXT:    s_mov_b32 s2, s4
157; GFX10-NEXT:    s_mov_b32 s3, s5
158; GFX10-NEXT:    s_mov_b32 s4, s6
159; GFX10-NEXT:    s_mov_b32 s5, s7
160; GFX10-NEXT:    s_mov_b32 s6, s8
161; GFX10-NEXT:    s_mov_b32 s7, s9
162; GFX10-NEXT:    image_load v[0:3], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm
163; GFX10-NEXT:    s_waitcnt vmcnt(0)
164; GFX10-NEXT:    ; return to shader part epilog
165main_body:
166  %v = call <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
167  ret <4 x float> %v
168}
169
170define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %u) {
171; GFX9-LABEL: load_mip_cube:
172; GFX9:       ; %bb.0: ; %main_body
173; GFX9-NEXT:    s_mov_b32 s0, s2
174; GFX9-NEXT:    s_mov_b32 s1, s3
175; GFX9-NEXT:    s_mov_b32 s2, s4
176; GFX9-NEXT:    s_mov_b32 s3, s5
177; GFX9-NEXT:    s_mov_b32 s4, s6
178; GFX9-NEXT:    s_mov_b32 s5, s7
179; GFX9-NEXT:    s_mov_b32 s6, s8
180; GFX9-NEXT:    s_mov_b32 s7, s9
181; GFX9-NEXT:    image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm da
182; GFX9-NEXT:    s_waitcnt vmcnt(0)
183; GFX9-NEXT:    ; return to shader part epilog
184;
185; GFX10-LABEL: load_mip_cube:
186; GFX10:       ; %bb.0: ; %main_body
187; GFX10-NEXT:    s_mov_b32 s0, s2
188; GFX10-NEXT:    s_mov_b32 s1, s3
189; GFX10-NEXT:    s_mov_b32 s2, s4
190; GFX10-NEXT:    s_mov_b32 s3, s5
191; GFX10-NEXT:    s_mov_b32 s4, s6
192; GFX10-NEXT:    s_mov_b32 s5, s7
193; GFX10-NEXT:    s_mov_b32 s6, s8
194; GFX10-NEXT:    s_mov_b32 s7, s9
195; GFX10-NEXT:    image_load v[0:3], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm
196; GFX10-NEXT:    s_waitcnt vmcnt(0)
197; GFX10-NEXT:    ; return to shader part epilog
198main_body:
199  %v = call <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
200  ret <4 x float> %v
201}
202
203define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
204; GFX9-LABEL: store_mip_1d:
205; GFX9:       ; %bb.0: ; %main_body
206; GFX9-NEXT:    s_mov_b32 s0, s2
207; GFX9-NEXT:    s_mov_b32 s1, s3
208; GFX9-NEXT:    s_mov_b32 s2, s4
209; GFX9-NEXT:    s_mov_b32 s3, s5
210; GFX9-NEXT:    s_mov_b32 s4, s6
211; GFX9-NEXT:    s_mov_b32 s5, s7
212; GFX9-NEXT:    s_mov_b32 s6, s8
213; GFX9-NEXT:    s_mov_b32 s7, s9
214; GFX9-NEXT:    image_store v[0:3], v4, s[0:7] dmask:0xf unorm
215; GFX9-NEXT:    s_endpgm
216;
217; GFX10-LABEL: store_mip_1d:
218; GFX10:       ; %bb.0: ; %main_body
219; GFX10-NEXT:    s_mov_b32 s0, s2
220; GFX10-NEXT:    s_mov_b32 s1, s3
221; GFX10-NEXT:    s_mov_b32 s2, s4
222; GFX10-NEXT:    s_mov_b32 s3, s5
223; GFX10-NEXT:    s_mov_b32 s4, s6
224; GFX10-NEXT:    s_mov_b32 s5, s7
225; GFX10-NEXT:    s_mov_b32 s6, s8
226; GFX10-NEXT:    s_mov_b32 s7, s9
227; GFX10-NEXT:    image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
228; GFX10-NEXT:    s_endpgm
229main_body:
230  call void @llvm.amdgcn.image.store.mip.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
231  ret void
232}
233
234define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {
235; GFX9-LABEL: store_mip_2d:
236; GFX9:       ; %bb.0: ; %main_body
237; GFX9-NEXT:    s_mov_b32 s0, s2
238; GFX9-NEXT:    s_mov_b32 s1, s3
239; GFX9-NEXT:    s_mov_b32 s2, s4
240; GFX9-NEXT:    s_mov_b32 s3, s5
241; GFX9-NEXT:    s_mov_b32 s4, s6
242; GFX9-NEXT:    s_mov_b32 s5, s7
243; GFX9-NEXT:    s_mov_b32 s6, s8
244; GFX9-NEXT:    s_mov_b32 s7, s9
245; GFX9-NEXT:    image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm
246; GFX9-NEXT:    s_endpgm
247;
248; GFX10-LABEL: store_mip_2d:
249; GFX10:       ; %bb.0: ; %main_body
250; GFX10-NEXT:    s_mov_b32 s0, s2
251; GFX10-NEXT:    s_mov_b32 s1, s3
252; GFX10-NEXT:    s_mov_b32 s2, s4
253; GFX10-NEXT:    s_mov_b32 s3, s5
254; GFX10-NEXT:    s_mov_b32 s4, s6
255; GFX10-NEXT:    s_mov_b32 s5, s7
256; GFX10-NEXT:    s_mov_b32 s6, s8
257; GFX10-NEXT:    s_mov_b32 s7, s9
258; GFX10-NEXT:    image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
259; GFX10-NEXT:    s_endpgm
260main_body:
261  call void @llvm.amdgcn.image.store.mip.2d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
262  ret void
263}
264
265define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %u) {
266; GFX9-LABEL: store_mip_3d:
267; GFX9:       ; %bb.0: ; %main_body
268; GFX9-NEXT:    s_mov_b32 s0, s2
269; GFX9-NEXT:    s_mov_b32 s1, s3
270; GFX9-NEXT:    s_mov_b32 s2, s4
271; GFX9-NEXT:    s_mov_b32 s3, s5
272; GFX9-NEXT:    s_mov_b32 s4, s6
273; GFX9-NEXT:    s_mov_b32 s5, s7
274; GFX9-NEXT:    s_mov_b32 s6, s8
275; GFX9-NEXT:    s_mov_b32 s7, s9
276; GFX9-NEXT:    image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm
277; GFX9-NEXT:    s_endpgm
278;
279; GFX10-LABEL: store_mip_3d:
280; GFX10:       ; %bb.0: ; %main_body
281; GFX10-NEXT:    s_mov_b32 s0, s2
282; GFX10-NEXT:    s_mov_b32 s1, s3
283; GFX10-NEXT:    s_mov_b32 s2, s4
284; GFX10-NEXT:    s_mov_b32 s3, s5
285; GFX10-NEXT:    s_mov_b32 s4, s6
286; GFX10-NEXT:    s_mov_b32 s5, s7
287; GFX10-NEXT:    s_mov_b32 s6, s8
288; GFX10-NEXT:    s_mov_b32 s7, s9
289; GFX10-NEXT:    image_store v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm
290; GFX10-NEXT:    s_endpgm
291main_body:
292  call void @llvm.amdgcn.image.store.mip.3d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
293  ret void
294}
295
296define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {
297; GFX9-LABEL: store_mip_1darray:
298; GFX9:       ; %bb.0: ; %main_body
299; GFX9-NEXT:    s_mov_b32 s0, s2
300; GFX9-NEXT:    s_mov_b32 s1, s3
301; GFX9-NEXT:    s_mov_b32 s2, s4
302; GFX9-NEXT:    s_mov_b32 s3, s5
303; GFX9-NEXT:    s_mov_b32 s4, s6
304; GFX9-NEXT:    s_mov_b32 s5, s7
305; GFX9-NEXT:    s_mov_b32 s6, s8
306; GFX9-NEXT:    s_mov_b32 s7, s9
307; GFX9-NEXT:    image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm da
308; GFX9-NEXT:    s_endpgm
309;
310; GFX10-LABEL: store_mip_1darray:
311; GFX10:       ; %bb.0: ; %main_body
312; GFX10-NEXT:    s_mov_b32 s0, s2
313; GFX10-NEXT:    s_mov_b32 s1, s3
314; GFX10-NEXT:    s_mov_b32 s2, s4
315; GFX10-NEXT:    s_mov_b32 s3, s5
316; GFX10-NEXT:    s_mov_b32 s4, s6
317; GFX10-NEXT:    s_mov_b32 s5, s7
318; GFX10-NEXT:    s_mov_b32 s6, s8
319; GFX10-NEXT:    s_mov_b32 s7, s9
320; GFX10-NEXT:    image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm
321; GFX10-NEXT:    s_endpgm
322main_body:
323  call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
324  ret void
325}
326
327define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %u) {
328; GFX9-LABEL: store_mip_2darray:
329; GFX9:       ; %bb.0: ; %main_body
330; GFX9-NEXT:    s_mov_b32 s0, s2
331; GFX9-NEXT:    s_mov_b32 s1, s3
332; GFX9-NEXT:    s_mov_b32 s2, s4
333; GFX9-NEXT:    s_mov_b32 s3, s5
334; GFX9-NEXT:    s_mov_b32 s4, s6
335; GFX9-NEXT:    s_mov_b32 s5, s7
336; GFX9-NEXT:    s_mov_b32 s6, s8
337; GFX9-NEXT:    s_mov_b32 s7, s9
338; GFX9-NEXT:    image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm da
339; GFX9-NEXT:    s_endpgm
340;
341; GFX10-LABEL: store_mip_2darray:
342; GFX10:       ; %bb.0: ; %main_body
343; GFX10-NEXT:    s_mov_b32 s0, s2
344; GFX10-NEXT:    s_mov_b32 s1, s3
345; GFX10-NEXT:    s_mov_b32 s2, s4
346; GFX10-NEXT:    s_mov_b32 s3, s5
347; GFX10-NEXT:    s_mov_b32 s4, s6
348; GFX10-NEXT:    s_mov_b32 s5, s7
349; GFX10-NEXT:    s_mov_b32 s6, s8
350; GFX10-NEXT:    s_mov_b32 s7, s9
351; GFX10-NEXT:    image_store v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm
352; GFX10-NEXT:    s_endpgm
353main_body:
354  call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
355  ret void
356}
357
358define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %u) {
359; GFX9-LABEL: store_mip_cube:
360; GFX9:       ; %bb.0: ; %main_body
361; GFX9-NEXT:    s_mov_b32 s0, s2
362; GFX9-NEXT:    s_mov_b32 s1, s3
363; GFX9-NEXT:    s_mov_b32 s2, s4
364; GFX9-NEXT:    s_mov_b32 s3, s5
365; GFX9-NEXT:    s_mov_b32 s4, s6
366; GFX9-NEXT:    s_mov_b32 s5, s7
367; GFX9-NEXT:    s_mov_b32 s6, s8
368; GFX9-NEXT:    s_mov_b32 s7, s9
369; GFX9-NEXT:    image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm da
370; GFX9-NEXT:    s_endpgm
371;
372; GFX10-LABEL: store_mip_cube:
373; GFX10:       ; %bb.0: ; %main_body
374; GFX10-NEXT:    s_mov_b32 s0, s2
375; GFX10-NEXT:    s_mov_b32 s1, s3
376; GFX10-NEXT:    s_mov_b32 s2, s4
377; GFX10-NEXT:    s_mov_b32 s3, s5
378; GFX10-NEXT:    s_mov_b32 s4, s6
379; GFX10-NEXT:    s_mov_b32 s5, s7
380; GFX10-NEXT:    s_mov_b32 s6, s8
381; GFX10-NEXT:    s_mov_b32 s7, s9
382; GFX10-NEXT:    image_store v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm
383; GFX10-NEXT:    s_endpgm
384main_body:
385  call void @llvm.amdgcn.image.store.mip.cube.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
386  ret void
387}
388
389declare <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
390declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
391declare <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
392declare <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
393declare <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
394declare <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
395declare void @llvm.amdgcn.image.store.mip.1d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1
396declare void @llvm.amdgcn.image.store.mip.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1
397declare void @llvm.amdgcn.image.store.mip.3d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1
398declare void @llvm.amdgcn.image.store.mip.cube.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1
399declare void @llvm.amdgcn.image.store.mip.1darray.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1
400declare void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1
401
402attributes #0 = { nounwind readonly }
403attributes #1 = { nounwind writeonly }
404