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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX6 %s
3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX6 %s
4# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
5
6---
7name:            add_s32
8legalized:       true
9regBankSelected: true
10
11body: |
12  bb.0:
13    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
14
15
16    ; GFX6-LABEL: name: add_s32
17    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
18    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
19    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
20    ; GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
21    ; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
22    ; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_CO_U32_e64 [[S_ADD_I32_]], %7, 0, implicit $exec
23    ; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_CO_U32_e64 %8, [[COPY2]], 0, implicit $exec
24    ; GFX6: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit %7, implicit %8, implicit %9
25    ; GFX9-LABEL: name: add_s32
26    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
27    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
28    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
29    ; GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
30    ; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
31    ; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_I32_]], [[V_ADD_U32_e64_]], 0, implicit $exec
32    ; GFX9: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec
33    ; GFX9: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_2]]
34    %0:sgpr(s32) = COPY $sgpr0
35    %1:sgpr(s32) = COPY $sgpr1
36    %2:vgpr(s32) = COPY $vgpr0
37    %3:vgpr(p1) = COPY $vgpr3_vgpr4
38    %4:sgpr(s32) = G_CONSTANT i32 1
39    %5:sgpr(s32) = G_CONSTANT i32 4096
40
41    ; add ss
42    %6:sgpr(s32) = G_ADD %0, %1
43
44    ; add vs
45    %7:vgpr(s32) = G_ADD %2, %6
46
47    ; add sv
48    %8:vgpr(s32) = G_ADD %6, %7
49
50    ; add vv
51    %9:vgpr(s32) = G_ADD %8, %2
52
53    S_ENDPGM 0, implicit %6, implicit %7, implicit %8, implicit %9
54
55...
56
57---
58name:            add_neg_inline_const_64_to_sub_s32_s
59legalized:       true
60regBankSelected: true
61tracksRegLiveness: true
62
63body: |
64  bb.0:
65    liveins: $sgpr0
66
67    ; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_s
68    ; GFX6: liveins: $sgpr0
69    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
70    ; GFX6: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
71    ; GFX6: S_ENDPGM 0, implicit [[S_SUB_I32_]]
72    ; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_s
73    ; GFX9: liveins: $sgpr0
74    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
75    ; GFX9: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
76    ; GFX9: S_ENDPGM 0, implicit [[S_SUB_I32_]]
77    %0:sgpr(s32) = COPY $sgpr0
78    %1:sgpr(s32) = G_CONSTANT i32 -64
79    %2:sgpr(s32) = G_ADD %0, %1
80    S_ENDPGM 0, implicit %2
81
82...
83
84---
85name:            add_neg_inline_const_64_to_sub_s32_v
86legalized:       true
87regBankSelected: true
88tracksRegLiveness: true
89
90body: |
91  bb.0:
92    liveins: $vgpr0
93
94    ; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_v
95    ; GFX6: liveins: $vgpr0
96    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
97    ; GFX6: %2:vgpr_32, dead %3:sreg_64 = V_SUB_CO_U32_e64 [[COPY]], 64, 0, implicit $exec
98    ; GFX6: S_ENDPGM 0, implicit %2
99    ; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_v
100    ; GFX9: liveins: $vgpr0
101    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
102    ; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY]], 64, 0, implicit $exec
103    ; GFX9: S_ENDPGM 0, implicit [[V_SUB_U32_e64_]]
104    %0:vgpr(s32) = COPY $vgpr0
105    %1:vgpr(s32) = G_CONSTANT i32 -64
106    %2:vgpr(s32) = G_ADD %0, %1
107    S_ENDPGM 0, implicit %2
108
109...
110
111---
112name:            add_neg_inline_const_16_to_sub_s32_s
113legalized:       true
114regBankSelected: true
115tracksRegLiveness: true
116
117body: |
118  bb.0:
119    liveins: $sgpr0
120
121    ; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_s
122    ; GFX6: liveins: $sgpr0
123    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
124    ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
125    ; GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
126    ; GFX6: S_ENDPGM 0, implicit [[S_ADD_I32_]]
127    ; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_s
128    ; GFX9: liveins: $sgpr0
129    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
130    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
131    ; GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
132    ; GFX9: S_ENDPGM 0, implicit [[S_ADD_I32_]]
133    %0:sgpr(s32) = COPY $sgpr0
134    %1:sgpr(s32) = G_CONSTANT i32 16
135    %2:sgpr(s32) = G_ADD %0, %1
136    S_ENDPGM 0, implicit %2
137
138...
139
140---
141name:            add_neg_inline_const_16_to_sub_s32_v
142legalized:       true
143regBankSelected: true
144tracksRegLiveness: true
145
146body: |
147  bb.0:
148    liveins: $vgpr0
149
150    ; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_v
151    ; GFX6: liveins: $vgpr0
152    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
153    ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
154    ; GFX6: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
155    ; GFX6: S_ENDPGM 0, implicit %2
156    ; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_v
157    ; GFX9: liveins: $vgpr0
158    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
159    ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
160    ; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
161    ; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
162    %0:vgpr(s32) = COPY $vgpr0
163    %1:vgpr(s32) = G_CONSTANT i32 16
164    %2:vgpr(s32) = G_ADD %0, %1
165    S_ENDPGM 0, implicit %2
166
167...
168