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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5
6name: ds_swizzle_0
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10
11
12body: |
13  bb.0:
14    liveins: $vgpr0
15    ; CHECK-LABEL: name: ds_swizzle_0
16    ; CHECK: liveins: $vgpr0
17    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
18    ; CHECK: [[DS_SWIZZLE_B32_:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[COPY]], 0, 0, implicit $exec
19    ; CHECK: S_ENDPGM 0, implicit [[DS_SWIZZLE_B32_]]
20    %0:vgpr(s32) = COPY $vgpr0
21    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ds.swizzle), %0, 0
22    S_ENDPGM 0, implicit %1
23
24...
25
26---
27
28name: ds_swizzle_65535
29legalized:       true
30regBankSelected: true
31tracksRegLiveness: true
32
33
34body: |
35  bb.0:
36    liveins: $vgpr0
37    ; CHECK-LABEL: name: ds_swizzle_65535
38    ; CHECK: liveins: $vgpr0
39    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
40    ; CHECK: [[DS_SWIZZLE_B32_:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[COPY]], 65535, 0, implicit $exec
41    ; CHECK: S_ENDPGM 0, implicit [[DS_SWIZZLE_B32_]]
42    %0:vgpr(s32) = COPY $vgpr0
43    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ds.swizzle), %0, 65535
44    S_ENDPGM 0, implicit %1
45
46...
47