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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
4# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*'  %s -o /dev/null 2>&1 | FileCheck -check-prefix=VI-ERR %s
5# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*'  %s -o /dev/null 2>&1 | FileCheck -check-prefix=VI-ERR %s
6
7# VI-ERR: remark: <unknown>:0:0: cannot select: %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0:sgpr(s32) (in function: rsq_clamp_s32_vs)
8# VI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0:vgpr(s32) (in function: rsq_clamp_s32_vv)
9
10---
11name: rsq_clamp_s32_vs
12legalized: true
13regBankSelected: true
14tracksRegLiveness: true
15
16body: |
17  bb.0:
18    liveins: $sgpr0
19
20    ; CHECK-LABEL: name: rsq_clamp_s32_vs
21    ; CHECK: liveins: $sgpr0
22    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
23    ; CHECK: %1:vgpr_32 = nofpexcept V_RSQ_CLAMP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
24    ; CHECK: S_ENDPGM 0, implicit %1
25    %0:sgpr(s32) = COPY $sgpr0
26    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0
27    S_ENDPGM 0, implicit %1
28...
29
30---
31name: rsq_clamp_s32_vv
32legalized: true
33regBankSelected: true
34tracksRegLiveness: true
35
36body: |
37  bb.0:
38    liveins: $vgpr0
39
40    ; CHECK-LABEL: name: rsq_clamp_s32_vv
41    ; CHECK: liveins: $vgpr0
42    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
43    ; CHECK: %1:vgpr_32 = nofpexcept V_RSQ_CLAMP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
44    ; CHECK: S_ENDPGM 0, implicit %1
45    %0:vgpr(s32) = COPY $vgpr0
46    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0
47    S_ENDPGM 0, implicit %1
48...
49