1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck %s 3 4--- 5name: ptrmask_p3_s32_sgpr_sgpr_sgpr 6legalized: true 7regBankSelected: true 8 9body: | 10 bb.0: 11 liveins: $sgpr0, $sgpr1 12 13 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_sgpr 14 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 15 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 16 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc 17 ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] 18 %0:sgpr(p3) = COPY $sgpr0 19 %1:sgpr(s32) = COPY $sgpr1 20 %2:sgpr(p3) = G_PTRMASK %0, %1 21 S_ENDPGM 0, implicit %2 22 23... 24 25--- 26name: ptrmask_p3_s32_sgpr_sgpr_0xf0f0f0f0 27legalized: true 28regBankSelected: true 29 30body: | 31 bb.0: 32 liveins: $sgpr0 33 34 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0xf0f0f0f0 35 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 36 ; CHECK: %const:sreg_32 = S_MOV_B32 -252645136 37 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc 38 ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] 39 %0:sgpr(p3) = COPY $sgpr0 40 %const:sgpr(s32) = G_CONSTANT i32 -252645136 41 %1:sgpr(p3) = G_PTRMASK %0, %const 42 S_ENDPGM 0, implicit %1 43 44... 45 46--- 47name: ptrmask_p3_s32_sgpr_sgpr_0xffffffff 48legalized: true 49regBankSelected: true 50 51body: | 52 bb.0: 53 liveins: $sgpr0 54 55 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0xffffffff 56 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 57 ; CHECK: %const:sreg_32 = S_MOV_B32 -1 58 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc 59 ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] 60 %0:sgpr(p3) = COPY $sgpr0 61 %const:sgpr(s32) = G_CONSTANT i32 -1 62 %1:sgpr(p3) = G_PTRMASK %0, %const 63 S_ENDPGM 0, implicit %1 64 65... 66 67--- 68name: ptrmask_p3_s32_sgpr_sgpr_0x00000000 69legalized: true 70regBankSelected: true 71 72body: | 73 bb.0: 74 liveins: $sgpr0 75 76 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0x00000000 77 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 78 ; CHECK: %const:sreg_32 = S_MOV_B32 0 79 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc 80 ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] 81 %0:sgpr(p3) = COPY $sgpr0 82 %const:sgpr(s32) = G_CONSTANT i32 0 83 %1:sgpr(p3) = G_PTRMASK %0, %const 84 S_ENDPGM 0, implicit %1 85 86... 87 88--- 89name: ptrmask_p3_s32_sgpr_sgpr_clearhi1 90legalized: true 91regBankSelected: true 92 93body: | 94 bb.0: 95 liveins: $sgpr0 96 97 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearhi1 98 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 99 ; CHECK: %const:sreg_32 = S_MOV_B32 -2147483648 100 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc 101 ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] 102 %0:sgpr(p3) = COPY $sgpr0 103 %const:sgpr(s32) = G_CONSTANT i32 -2147483648 104 %1:sgpr(p3) = G_PTRMASK %0, %const 105 S_ENDPGM 0, implicit %1 106 107... 108 109--- 110name: ptrmask_p3_s32_sgpr_sgpr_clearhi2 111legalized: true 112regBankSelected: true 113 114body: | 115 bb.0: 116 liveins: $sgpr0 117 118 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearhi2 119 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 120 ; CHECK: %const:sreg_32 = S_MOV_B32 -1073741824 121 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc 122 ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] 123 %0:sgpr(p3) = COPY $sgpr0 124 %const:sgpr(s32) = G_CONSTANT i32 -1073741824 125 %1:sgpr(p3) = G_PTRMASK %0, %const 126 S_ENDPGM 0, implicit %1 127 128... 129 130--- 131name: ptrmask_p3_s32_sgpr_sgpr_clearlo1 132legalized: true 133regBankSelected: true 134 135body: | 136 bb.0: 137 liveins: $sgpr0 138 139 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo1 140 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 141 ; CHECK: %const:sreg_32 = S_MOV_B32 -2 142 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc 143 ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] 144 %0:sgpr(p3) = COPY $sgpr0 145 %const:sgpr(s32) = G_CONSTANT i32 -2 146 %1:sgpr(p3) = G_PTRMASK %0, %const 147 S_ENDPGM 0, implicit %1 148 149... 150 151--- 152name: ptrmask_p3_s32_sgpr_sgpr_clearlo2 153legalized: true 154regBankSelected: true 155 156body: | 157 bb.0: 158 liveins: $sgpr0 159 160 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo2 161 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 162 ; CHECK: %const:sreg_32 = S_MOV_B32 -4 163 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc 164 ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] 165 %0:sgpr(p3) = COPY $sgpr0 166 %const:sgpr(s32) = G_CONSTANT i32 -4 167 %1:sgpr(p3) = G_PTRMASK %0, %const 168 S_ENDPGM 0, implicit %1 169 170... 171 172--- 173name: ptrmask_p3_s32_sgpr_sgpr_clearlo3 174legalized: true 175regBankSelected: true 176 177body: | 178 bb.0: 179 liveins: $sgpr0 180 181 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo3 182 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 183 ; CHECK: %const:sreg_32 = S_MOV_B32 -8 184 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc 185 ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] 186 %0:sgpr(p3) = COPY $sgpr0 187 %const:sgpr(s32) = G_CONSTANT i32 -8 188 %1:sgpr(p3) = G_PTRMASK %0, %const 189 S_ENDPGM 0, implicit %1 190 191... 192 193--- 194name: ptrmask_p3_s32_sgpr_sgpr_clearlo4 195legalized: true 196regBankSelected: true 197 198body: | 199 bb.0: 200 liveins: $sgpr0 201 202 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo4 203 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 204 ; CHECK: %const:sreg_32 = S_MOV_B32 -16 205 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc 206 ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] 207 %0:sgpr(p3) = COPY $sgpr0 208 %const:sgpr(s32) = G_CONSTANT i32 -16 209 %1:sgpr(p3) = G_PTRMASK %0, %const 210 S_ENDPGM 0, implicit %1 211 212... 213 214--- 215name: ptrmask_p3_s32_sgpr_sgpr_clearlo29 216legalized: true 217regBankSelected: true 218 219body: | 220 bb.0: 221 liveins: $sgpr0 222 223 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo29 224 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 225 ; CHECK: %const:sreg_32 = S_MOV_B32 -536870912 226 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc 227 ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] 228 %0:sgpr(p3) = COPY $sgpr0 229 %const:sgpr(s32) = G_CONSTANT i32 -536870912 230 %1:sgpr(p3) = G_PTRMASK %0, %const 231 S_ENDPGM 0, implicit %1 232 233... 234 235--- 236name: ptrmask_p0_s64_sgpr_sgpr_sgpr 237legalized: true 238regBankSelected: true 239 240body: | 241 bb.0: 242 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 243 244 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr 245 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 246 ; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 247 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 248 ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 249 ; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0 250 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[COPY4]], implicit-def $scc 251 ; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1 252 ; CHECK: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY3]], [[COPY5]], implicit-def $scc 253 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[S_AND_B32_1]], %subreg.sub1 254 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 255 %0:sgpr(p0) = COPY $sgpr0_sgpr1 256 %1:sgpr(s64) = COPY $sgpr2_sgpr3 257 %2:sgpr(p0) = G_PTRMASK %0, %1 258 S_ENDPGM 0, implicit %2 259 260... 261 262--- 263name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xffffffffffffffff 264legalized: true 265regBankSelected: true 266 267body: | 268 bb.0: 269 liveins: $sgpr0_sgpr1 270 271 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xffffffffffffffff 272 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 273 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 274 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 275 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1 276 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 277 %0:sgpr(p0) = COPY $sgpr0_sgpr1 278 %1:sgpr(s64) = G_CONSTANT i64 -1 279 %2:sgpr(p0) = G_PTRMASK %0, %1 280 S_ENDPGM 0, implicit %2 281 282... 283 284--- 285name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0x0000000000000000 286legalized: true 287regBankSelected: true 288 289body: | 290 bb.0: 291 liveins: $sgpr0_sgpr1 292 293 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0x0000000000000000 294 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 295 ; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 296 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 297 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 298 ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B64_]].sub0 299 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc 300 ; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B64_]].sub1 301 ; CHECK: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[COPY4]], implicit-def $scc 302 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[S_AND_B32_1]], %subreg.sub1 303 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 304 %0:sgpr(p0) = COPY $sgpr0_sgpr1 305 %1:sgpr(s64) = G_CONSTANT i64 0 306 %2:sgpr(p0) = G_PTRMASK %0, %1 307 S_ENDPGM 0, implicit %2 308 309... 310 311--- 312name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xf0f0f0f0f0f0f0f0 313legalized: true 314regBankSelected: true 315 316body: | 317 bb.0: 318 liveins: $sgpr0_sgpr1 319 320 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xf0f0f0f0f0f0f0f0 321 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 322 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4042322160 323 ; CHECK: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -252645136 324 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 325 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 326 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 327 ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0 328 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc 329 ; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1 330 ; CHECK: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[COPY4]], implicit-def $scc 331 ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[S_AND_B32_1]], %subreg.sub1 332 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE1]] 333 %0:sgpr(p0) = COPY $sgpr0_sgpr1 334 %1:sgpr(s64) = G_CONSTANT i64 -1085102592571150096 335 %2:sgpr(p0) = G_PTRMASK %0, %1 336 S_ENDPGM 0, implicit %2 337 338... 339 340--- 341name: ptrmask_p0_s64_sgpr_sgpr_clearhi1 342legalized: true 343regBankSelected: true 344 345body: | 346 bb.0: 347 liveins: $sgpr0_sgpr1 348 349 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearhi1 350 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 351 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 352 ; CHECK: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648 353 ; CHECK: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 354 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 355 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 356 ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0 357 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc 358 ; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY %const.sub1 359 ; CHECK: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[COPY4]], implicit-def $scc 360 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[S_AND_B32_1]], %subreg.sub1 361 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 362 %0:sgpr(p0) = COPY $sgpr0_sgpr1 363 %const:sgpr(s64) = G_CONSTANT i64 -9223372036854775808 364 %1:sgpr(p0) = G_PTRMASK %0, %const 365 S_ENDPGM 0, implicit %1 366 367... 368 369--- 370name: ptrmask_p0_s64_sgpr_sgpr_clearhi32 371legalized: true 372regBankSelected: true 373 374body: | 375 bb.0: 376 liveins: $sgpr0_sgpr1 377 378 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearhi32 379 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 380 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 381 ; CHECK: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 382 ; CHECK: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 383 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 384 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 385 ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0 386 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc 387 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 388 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 389 %0:sgpr(p0) = COPY $sgpr0_sgpr1 390 %const:sgpr(s64) = G_CONSTANT i64 -4294967296 391 %1:sgpr(p0) = G_PTRMASK %0, %const 392 S_ENDPGM 0, implicit %1 393 394... 395 396--- 397name: ptrmask_p0_s64_sgpr_sgpr_clear_32 398legalized: true 399regBankSelected: true 400 401body: | 402 bb.0: 403 liveins: $sgpr0_sgpr1 404 405 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clear_32 406 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 407 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 408 ; CHECK: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1 409 ; CHECK: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 410 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 411 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 412 ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0 413 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc 414 ; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY %const.sub1 415 ; CHECK: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[COPY4]], implicit-def $scc 416 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[S_AND_B32_1]], %subreg.sub1 417 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 418 %0:sgpr(p0) = COPY $sgpr0_sgpr1 419 %const:sgpr(s64) = G_CONSTANT i64 4294967296 420 %1:sgpr(p0) = G_PTRMASK %0, %const 421 S_ENDPGM 0, implicit %1 422 423... 424 425--- 426name: ptrmask_p0_s64_sgpr_sgpr_clearlo1 427legalized: true 428regBankSelected: true 429 430body: | 431 bb.0: 432 liveins: $sgpr0_sgpr1 433 434 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo1 435 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 436 ; CHECK: %const:sreg_64 = S_MOV_B64 -2 437 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 438 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 439 ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0 440 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc 441 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 442 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 443 %0:sgpr(p0) = COPY $sgpr0_sgpr1 444 %const:sgpr(s64) = G_CONSTANT i64 -2 445 %1:sgpr(p0) = G_PTRMASK %0, %const 446 S_ENDPGM 0, implicit %1 447 448... 449 450--- 451name: ptrmask_p0_s64_sgpr_sgpr_clearlo2 452legalized: true 453regBankSelected: true 454 455body: | 456 bb.0: 457 liveins: $sgpr0_sgpr1 458 459 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo2 460 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 461 ; CHECK: %const:sreg_64 = S_MOV_B64 -4 462 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 463 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 464 ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0 465 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc 466 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 467 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 468 %0:sgpr(p0) = COPY $sgpr0_sgpr1 469 %const:sgpr(s64) = G_CONSTANT i64 -4 470 %1:sgpr(p0) = G_PTRMASK %0, %const 471 S_ENDPGM 0, implicit %1 472 473... 474 475--- 476name: ptrmask_p0_s64_sgpr_sgpr_clearlo3 477legalized: true 478regBankSelected: true 479 480body: | 481 bb.0: 482 liveins: $sgpr0_sgpr1 483 484 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo3 485 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 486 ; CHECK: %const:sreg_64 = S_MOV_B64 -8 487 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 488 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 489 ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0 490 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc 491 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 492 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 493 %0:sgpr(p0) = COPY $sgpr0_sgpr1 494 %const:sgpr(s64) = G_CONSTANT i64 -8 495 %1:sgpr(p0) = G_PTRMASK %0, %const 496 S_ENDPGM 0, implicit %1 497 498... 499 500--- 501name: ptrmask_p0_s64_sgpr_sgpr_clearlo4 502legalized: true 503regBankSelected: true 504 505body: | 506 bb.0: 507 liveins: $sgpr0_sgpr1 508 509 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo4 510 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 511 ; CHECK: %const:sreg_64 = S_MOV_B64 -16 512 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 513 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 514 ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0 515 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc 516 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 517 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 518 %0:sgpr(p0) = COPY $sgpr0_sgpr1 519 %const:sgpr(s64) = G_CONSTANT i64 -16 520 %1:sgpr(p0) = G_PTRMASK %0, %const 521 S_ENDPGM 0, implicit %1 522 523... 524 525--- 526name: ptrmask_p0_s64_sgpr_sgpr_clearlo29 527legalized: true 528regBankSelected: true 529 530body: | 531 bb.0: 532 liveins: $sgpr0_sgpr1 533 534 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo29 535 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 536 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 3758096384 537 ; CHECK: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 538 ; CHECK: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 539 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 540 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 541 ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0 542 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc 543 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 544 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 545 %0:sgpr(p0) = COPY $sgpr0_sgpr1 546 %const:sgpr(s64) = G_CONSTANT i64 -536870912 547 %1:sgpr(p0) = G_PTRMASK %0, %const 548 S_ENDPGM 0, implicit %1 549 550... 551 552--- 553name: ptrmask_p3_vgpr_vgpr_0xf0f0f0f0 554legalized: true 555regBankSelected: true 556 557body: | 558 bb.0: 559 liveins: $vgpr0 560 561 ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_0xf0f0f0f0 562 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 563 ; CHECK: %const:vgpr_32 = V_MOV_B32_e32 -252645136, implicit $exec 564 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec 565 ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]] 566 %0:vgpr(p3) = COPY $vgpr0 567 %const:vgpr(s32) = G_CONSTANT i32 -252645136 568 %1:vgpr(p3) = G_PTRMASK %0, %const 569 S_ENDPGM 0, implicit %1 570 571... 572 573--- 574name: ptrmask_p3_vgpr_vgpr_clearlo1 575legalized: true 576regBankSelected: true 577 578body: | 579 bb.0: 580 liveins: $vgpr0 581 582 ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo1 583 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 584 ; CHECK: %const:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec 585 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec 586 ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]] 587 %0:vgpr(p3) = COPY $vgpr0 588 %const:vgpr(s32) = G_CONSTANT i32 -2 589 %1:vgpr(p3) = G_PTRMASK %0, %const 590 S_ENDPGM 0, implicit %1 591 592... 593 594--- 595name: ptrmask_p3_vgpr_vgpr_clearlo2 596legalized: true 597regBankSelected: true 598 599body: | 600 bb.0: 601 liveins: $vgpr0 602 603 ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo2 604 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 605 ; CHECK: %const:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec 606 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec 607 ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]] 608 %0:vgpr(p3) = COPY $vgpr0 609 %const:vgpr(s32) = G_CONSTANT i32 -4 610 %1:vgpr(p3) = G_PTRMASK %0, %const 611 S_ENDPGM 0, implicit %1 612 613... 614 615--- 616name: ptrmask_p3_vgpr_vgpr_clearlo3 617legalized: true 618regBankSelected: true 619 620body: | 621 bb.0: 622 liveins: $vgpr0 623 624 ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo3 625 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 626 ; CHECK: %const:vgpr_32 = V_MOV_B32_e32 -8, implicit $exec 627 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec 628 ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]] 629 %0:vgpr(p3) = COPY $vgpr0 630 %const:vgpr(s32) = G_CONSTANT i32 -8 631 %1:vgpr(p3) = G_PTRMASK %0, %const 632 S_ENDPGM 0, implicit %1 633 634... 635 636--- 637name: ptrmask_p3_vgpr_vgpr_clearlo4 638legalized: true 639regBankSelected: true 640 641body: | 642 bb.0: 643 liveins: $vgpr0 644 645 ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo4 646 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 647 ; CHECK: %const:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec 648 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec 649 ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]] 650 %0:vgpr(p3) = COPY $vgpr0 651 %const:vgpr(s32) = G_CONSTANT i32 -16 652 %1:vgpr(p3) = G_PTRMASK %0, %const 653 S_ENDPGM 0, implicit %1 654 655... 656 657--- 658name: ptrmask_p3_vgpr_vgpr_clearlo29 659legalized: true 660regBankSelected: true 661 662body: | 663 bb.0: 664 liveins: $vgpr0 665 666 ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo29 667 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 668 ; CHECK: %const:vgpr_32 = V_MOV_B32_e32 -536870912, implicit $exec 669 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec 670 ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]] 671 %0:vgpr(p3) = COPY $vgpr0 672 %const:vgpr(s32) = G_CONSTANT i32 -536870912 673 %1:vgpr(p3) = G_PTRMASK %0, %const 674 S_ENDPGM 0, implicit %1 675 676... 677 678--- 679name: ptrmask_p0_s64_vgpr_vgpr_vgpr 680legalized: true 681regBankSelected: true 682 683body: | 684 bb.0: 685 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 686 687 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_vgpr 688 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 689 ; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 690 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 691 ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 692 ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0 693 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], [[COPY4]], implicit $exec 694 ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1 695 ; CHECK: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY3]], [[COPY5]], implicit $exec 696 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1 697 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 698 %0:vgpr(p0) = COPY $vgpr0_vgpr1 699 %1:vgpr(s64) = COPY $vgpr2_vgpr3 700 %2:vgpr(p0) = G_PTRMASK %0, %1 701 S_ENDPGM 0, implicit %2 702 703... 704 705--- 706name: ptrmask_p0_s64_vgpr_vgpr_vgpr_0xf0f0f0f0f0f0f0f0 707legalized: true 708regBankSelected: true 709 710body: | 711 bb.0: 712 liveins: $vgpr0_vgpr1 713 714 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_vgpr_0xf0f0f0f0f0f0f0f0 715 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 716 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4042322160, implicit $exec 717 ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -252645136, implicit $exec 718 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1 719 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 720 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 721 ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0 722 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec 723 ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1 724 ; CHECK: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], [[COPY4]], implicit $exec 725 ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1 726 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE1]] 727 %0:vgpr(p0) = COPY $vgpr0_vgpr1 728 %1:vgpr(s64) = G_CONSTANT i64 -1085102592571150096 729 %2:vgpr(p0) = G_PTRMASK %0, %1 730 S_ENDPGM 0, implicit %2 731 732... 733 734--- 735name: ptrmask_p0_s64_vgpr_vgpr_clearlo1 736legalized: true 737regBankSelected: true 738 739body: | 740 bb.0: 741 liveins: $vgpr0_vgpr1 742 743 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo1 744 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 745 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967294, implicit $exec 746 ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec 747 ; CHECK: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1 748 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 749 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 750 ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0 751 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec 752 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1 753 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 754 %0:vgpr(p0) = COPY $vgpr0_vgpr1 755 %const:vgpr(s64) = G_CONSTANT i64 -2 756 %1:vgpr(p0) = G_PTRMASK %0, %const 757 S_ENDPGM 0, implicit %1 758 759... 760 761--- 762name: ptrmask_p0_s64_vgpr_vgpr_clearlo2 763legalized: true 764regBankSelected: true 765 766body: | 767 bb.0: 768 liveins: $vgpr0_vgpr1 769 770 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo2 771 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 772 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967292, implicit $exec 773 ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec 774 ; CHECK: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1 775 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 776 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 777 ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0 778 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec 779 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1 780 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 781 %0:vgpr(p0) = COPY $vgpr0_vgpr1 782 %const:vgpr(s64) = G_CONSTANT i64 -4 783 %1:vgpr(p0) = G_PTRMASK %0, %const 784 S_ENDPGM 0, implicit %1 785 786... 787 788--- 789name: ptrmask_p0_s64_vgpr_vgpr_clearlo3 790legalized: true 791regBankSelected: true 792 793body: | 794 bb.0: 795 liveins: $vgpr0_vgpr1 796 797 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo3 798 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 799 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967292, implicit $exec 800 ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec 801 ; CHECK: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1 802 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 803 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 804 ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0 805 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec 806 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1 807 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 808 %0:vgpr(p0) = COPY $vgpr0_vgpr1 809 %const:vgpr(s64) = G_CONSTANT i64 -4 810 %1:vgpr(p0) = G_PTRMASK %0, %const 811 S_ENDPGM 0, implicit %1 812 813... 814 815--- 816name: ptrmask_p0_s64_vgpr_vgpr_clearlo4 817legalized: true 818regBankSelected: true 819 820body: | 821 bb.0: 822 liveins: $vgpr0_vgpr1 823 824 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo4 825 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 826 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967280, implicit $exec 827 ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec 828 ; CHECK: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1 829 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 830 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 831 ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0 832 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec 833 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1 834 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 835 %0:vgpr(p0) = COPY $vgpr0_vgpr1 836 %const:vgpr(s64) = G_CONSTANT i64 -16 837 %1:vgpr(p0) = G_PTRMASK %0, %const 838 S_ENDPGM 0, implicit %1 839 840... 841 842--- 843name: ptrmask_p0_s64_vgpr_vgpr_clearlo29 844legalized: true 845regBankSelected: true 846 847body: | 848 bb.0: 849 liveins: $vgpr0_vgpr1 850 851 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo29 852 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 853 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3758096384, implicit $exec 854 ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec 855 ; CHECK: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1 856 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 857 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 858 ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0 859 ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec 860 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1 861 ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 862 %0:vgpr(p0) = COPY $vgpr0_vgpr1 863 %const:vgpr(s64) = G_CONSTANT i64 -536870912 864 %1:vgpr(p0) = G_PTRMASK %0, %const 865 S_ENDPGM 0, implicit %1 866 867... 868 869--- 870name: ptrmask_p3_vgpr_sgpr_clearlo2 871legalized: true 872regBankSelected: true 873 874body: | 875 bb.0: 876 liveins: $sgpr0 877 878 ; CHECK-LABEL: name: ptrmask_p3_vgpr_sgpr_clearlo2 879 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0 880 ; CHECK: %const:sgpr(s32) = G_CONSTANT i32 -4 881 ; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p3) = G_PTRMASK [[COPY]], %const(s32) 882 ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p3) 883 %0:sgpr(p3) = COPY $sgpr0 884 %const:sgpr(s32) = G_CONSTANT i32 -4 885 %1:vgpr(p3) = G_PTRMASK %0, %const 886 S_ENDPGM 0, implicit %1 887 888... 889 890--- 891name: ptrmask_p0_s64_vgpr_sgpr_clearlo2 892legalized: true 893regBankSelected: true 894 895body: | 896 bb.0: 897 liveins: $sgpr0_sgpr1 898 899 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_sgpr_clearlo2 900 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1 901 ; CHECK: %const:sgpr(s32) = G_CONSTANT i32 -4 902 ; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p0) = G_PTRMASK [[COPY]], %const(s32) 903 ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0) 904 %0:sgpr(p0) = COPY $sgpr0_sgpr1 905 %const:sgpr(s32) = G_CONSTANT i32 -4 906 %1:vgpr(p0) = G_PTRMASK %0, %const 907 S_ENDPGM 0, implicit %1 908 909... 910