1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s 3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s 4 5--- 6name: atomic_cmpxchg_local_i32 7 8body: | 9 bb.0: 10 liveins: $sgpr0, $sgpr1, $sgpr2 11 ; CHECK-LABEL: name: atomic_cmpxchg_local_i32 12 ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $sgpr0 13 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1 14 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr2 15 ; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p3), [[COPY1]], [[COPY2]] :: (load store seq_cst 4, addrspace 3) 16 %0:_(p3) = COPY $sgpr0 17 %1:_(s32) = COPY $sgpr1 18 %2:_(s32) = COPY $sgpr2 19 %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst 4, addrspace 3) 20... 21 22--- 23name: atomic_cmpxchg_local_i64 24 25body: | 26 bb.0: 27 liveins: $sgpr0, $sgpr1, $sgpr2 28 ; CHECK-LABEL: name: atomic_cmpxchg_local_i64 29 ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $sgpr0 30 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1 31 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr2 32 ; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p3), [[COPY1]], [[COPY2]] :: (load store seq_cst 8, addrspace 3) 33 %0:_(p3) = COPY $sgpr0 34 %1:_(s32) = COPY $sgpr1 35 %2:_(s32) = COPY $sgpr2 36 %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst 8, addrspace 3) 37... 38 39--- 40name: atomic_cmpxchg_global_i32 41 42body: | 43 bb.0: 44 liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3 45 ; CHECK-LABEL: name: atomic_cmpxchg_global_i32 46 ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $sgpr0_sgpr1 47 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2 48 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr3 49 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 50 ; CHECK: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p1), [[BUILD_VECTOR]] :: (load store seq_cst 4, addrspace 1) 51 %0:_(p1) = COPY $sgpr0_sgpr1 52 %1:_(s32) = COPY $sgpr2 53 %2:_(s32) = COPY $sgpr3 54 %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst 4, addrspace 1) 55... 56 57--- 58name: atomic_cmpxchg_global_i64 59 60body: | 61 bb.0: 62 liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3 63 ; CHECK-LABEL: name: atomic_cmpxchg_global_i64 64 ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $sgpr0_sgpr1 65 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2 66 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr3 67 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 68 ; CHECK: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p1), [[BUILD_VECTOR]] :: (load store seq_cst 8, addrspace 1) 69 %0:_(p1) = COPY $sgpr0_sgpr1 70 %1:_(s32) = COPY $sgpr2 71 %2:_(s32) = COPY $sgpr3 72 %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst 8, addrspace 1) 73... 74 75--- 76name: atomic_cmpxchg_flat_i32 77 78body: | 79 bb.0: 80 liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3 81 82 ; CHECK-LABEL: name: atomic_cmpxchg_flat_i32 83 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $sgpr0_sgpr1 84 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2 85 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr3 86 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 87 ; CHECK: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p0), [[BUILD_VECTOR]] :: (load store seq_cst 4) 88 %0:_(p0) = COPY $sgpr0_sgpr1 89 %1:_(s32) = COPY $sgpr2 90 %2:_(s32) = COPY $sgpr3 91 %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst 4, addrspace 0) 92... 93 94--- 95name: atomic_cmpxchg_flat_i64 96 97body: | 98 bb.0: 99 liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3 100 101 ; CHECK-LABEL: name: atomic_cmpxchg_flat_i64 102 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $sgpr0_sgpr1 103 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2 104 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr3 105 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 106 ; CHECK: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p0), [[BUILD_VECTOR]] :: (load store seq_cst 8) 107 %0:_(p0) = COPY $sgpr0_sgpr1 108 %1:_(s32) = COPY $sgpr2 109 %2:_(s32) = COPY $sgpr3 110 %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst 8, addrspace 0) 111... 112